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STE10/100
PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY (5V)
PRODUCT PREVIEW
1.0 DESCRIPTION The STE10/100 is a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application. It was designed with advanced CMOS technology to provide glueless 32-bit bus master interface for PCI bus, boot ROM interface, CSMA/CD protocol for Fast Ethernet, as well as the physical media interface for 100BASE-TX of IEEE802.3u and 10BASE-T of IEEE802.3. The auto-negotiation function is also supported for speed and duplex detection. The STE10/100 provides both half-duplex and fullduplex operation, as well as support for full-duplex flow control. It provides long FIFO buffers for transmission and receiving, and early interrupt mechanism to enhance performance. The STE10/100 also supports ACPI and PCI compliant power management function. 2.0 FEATURES
s
PQFP128 (14x20x2.7mm) ORDERING NUMBER: STE10/100
s s
PCI bus interface Rev. 2.2 compliant ACPI and PCI power management standard compliant Support PC99 wake on LAN
s
2.2 FIFO
s
Provides independent transmission and receiving FIFOs, each 2k bytes long Pre-fetches up to two transmit packets to minimize inter frame gap (IFG) to 0.96us Retransmits collided packet without reload from host memory within 64 bytes. Automatically retransmits FIFO under-run packet with maximum drain threshold until 3rd time retry failure without influencing the registers and transmit threshold of next packet.
2.1 Industry standard
s
IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant Support for IEEE802.3x flow control IEEE802.3u Auto-Negotiation support for 10BASE-T and 100BASE-TX
s
s s
s
Figure 1. STE10/100Block Diagram
DMA
MII Controller
Flow Control
Manchester Encoder
10 TX Filter Transmitter
125Mhz 25Mhz
4B/5B
Scrambler
Auto Negotiation
PCI Controller
Tx FiFo Rx FiFo
5B/4B
TX Freq. Synth. Adaptive Equalization
20Mhz
Descrambler
100 clock Recovery Manchester Decoder
MAC SubLaye MII Controller
BaseLine Restore
+ _
10 clock Recovery Link Polarity
September 1999
This is preliminary information on a new product now in development. Details are subject to change without notice.
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STE10/100
2.3 PCI I/F
s s s s
Provides 32-bit PCI bus master data transfer Supports PCI clock with frequency from 0Hz to 33MHz Supports network operation with PCI system clock from 20MHz to 33MHz Provides performance meter and PCI bus master latency timer for tuning the threshold to enhance the performance Provides burst transmit packet interrupt and transmit/receive early interrupt to reduce host CPU utilization As bus master, supports memory-read, memory-read-line, memory-read-multiple, memory-write, memory-write-and-invalidate command Supports big or little endian byte ordering
s
s
s
2.4 EEPROM/Boot ROM I/F
s s s s s
Provides writeable Flash ROM and EPROM as boot ROM, up to 128kB Provides PCI to access boot ROM by byte, word, or double word Re-writes Flash boot ROM through I/O port by programming register Provides serial interface for read/write 93C46 EEPROM Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency , and Minimum-Grand from the 64 byte contents of 93C46 after PCI reset de-asserted
2.5 MAC/Physical
s s s s s s s s s
Integrates the complete set of Physical layer 100BASE-TX and 10BASE-T functions Provides Full-duplex operation in both 100Mbps and 10Mbps modes Provides Auto-negotiation (NWAY) function of full/half duplex operation for both 10 and 100 Mbps Provides MLT-3 transceiver with DC restoration for Base-line wander compensation Provides transmit wave-shaper, receive filters, and adaptive equalizer Provides MAC and Transceiver (TXCVR) loop-back modes for diagnostic Built-in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder Supports external transmit transformer with 1.414:1 turn ratio Supports external receive transformer with 1:1 turn ratio
2.6 LED Display
s
Provides 2 LED display modes: 3 LED displays for 100Mbps (on) or 10Mbps (off) Link (Remains on when link ok) or Activity (Blinks at 10Hz when receiving or transmitting collision-free) FD (Remains on when in Full duplex mode) or when collision detected (Blinks at 20Hz) 4 LED displays for 100 Link (On when 100M link ok) 10 Link (On when 10M link ok) Activity (Blinks at 10Hz when receiving or transmitting) FD (Remains on when in Full duplex mode) or when collision detected (Blinks at 20Hz)
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2.7 Miscellaneous
s s s
ACPI and PCI compliant power management functions offer significant power-savings performance Provides general purpose timers 128-pin QFP package
Figure 2. System Diagram of the STE10/100
Serial EEPROM
Boot ROM
PCI Interface
STE10/100
Xfmr
Medium
LEDs
25 MHz Crystal
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3.0 PIN ASSIGNEMENT DIAGRAM Figure 3. Pin Connection
VDD-PCI VDD-PCI PCI-CLK VSS-PCI VSS-PCI AVSST AVDDR 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VDD-PCI VSS-PCI VDD-PCI AD-8 C-BEB0 AD-7 AD-6 AD-5 VSS-IR AD-4 BrA-4 BrA-5 BrA6 VSS-IR VSS-PCI BrA -0 BrA-1 BrA-2 BrA-3 VDD-IR BrA-7 AD-2 AD-1 AD-0 AD-3 N.C. VDD-IR VSS-IR AVSSR AVDDT
AD-30
AD-26
AD-27
AD-28
AD-29
AD-31
PME#
REQ#
GNT#
INTA#
RST#
TX+
RX+
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 AD-25 AD-24 C-BEB3 IDSEL VSS-PCI AD-23 AD-22 VDD-PCI AD-21 AD-20 VSS-PCI AD-19 AD-18 VDD-PCI AD-17 AD-16 C-BEB2 FRAME# VSS-PCI IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR VDD-PCI C-BEB1 AD-15 AD-14 VSS-PCI AD-13 AD-12 AD-11 AD-10 VSS-PCI AD-9 VDD-IR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 AVSSI IREF AVDDI AVDDX X1 X2 AVSSX AVDDREC AVSSREC VSS-IR LED M1/M2 LED M1/M2 LED M1/M2 VCC-detect VCC-detect BrA-16/LED M2 BrA-15 VDD-IR BrA-14 BrA-13 BrA-12 BrA-11 BrA-10 BrWE# BrOE# BrCS# EECS VSS-IR BrD-7/ECK BrD-6/EDI BrD-5/EDO BrD-4 BrD-3 BrD-2 BrD-1 BrD-0 BrA-9 BrA-8
RX-
TX-
D99TL443
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4.0 4. PIN DESCRIPTION Table 1. Pin Description
Pin No. Name Type Description
PCI bus Interface 113 114 INTA# RST# O/D I PCI interrupt request. STE10/100 asserts this signal when one of the interrupt event is set. PCI Reset signal to initialize the STE10/100. The RST signal should be asserted for at least 100s to ensure that the STE10/100 completes initialization. During the reset period, all the output pins of STE10/100 will be placed in a highimpedance state and all the O/D pins are floated. PCI clock input to STE10/100 for PCI Bus functions. The Bus signals are synchronized relative to the rising edge of PCI-CLK PCI-CLK must operate at a frequency in the range between 20MHz and 33MHz to ensure proper network operation PCI Bus Granted. This signal indicates that the STE10/100 has been granted ownership of the PCI Bus as a result of a Bus Request. PCI Bus Request. STE10/100 asserts this line when it needs access to the PCI Bus. The Power Management Event signal is an open drain, active low signal. The STE10/100 will assert PME# to indicate that a power management event has occurred. When WOL (bit 18 of CSR18) is set, the STE10/100 is placed in Wake On LAN mode. While in this mode, the STE10/100 will activate the PME# signal upon receipt of a Magic Packet frame from the network. In the Wake On LAN mode, when LWS (bit 17 of CSR18) is set, the LAN-WAKE signal follows HP's protocol; otherwise, it is IBM protocol. Multiplexed PCI Bus address/data pins
116
PCI-CLK
I
117 118 119
GNT# REQ# PME#
I O O OD
120,121 123,124 126,127 1,2 6,7 9,10 12,13 15,16 29,30 32~35 37 41 43,44 46,47 49,50 52,53 3 17 28 42 4 18 20
AD-31,30 AD-29,28 AD-27,26 AD-25,24 AD-23,22 AD-21,20 AD-19,18 AD-17,16 AD-15,14 AD-13~10 AD-9 AD-8 AD-7, 6 AD-5,4 AD-3,2 AD-1,0 C-BEB3 C-BEB2 C-BEB1 C-BEB0 IDSEL FRAME# IRDY#
I/O
I/O
Bus command and byte enable
I I/O I/O
Initialization Device Select. This signal is asserted when the host issues configuration cycles to the STE10/100. Asserted by PCI Bus master during bus tenure Master device is ready to begin data transaction
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Table 1. Pin Description
Pin No. 21 22 23 24 25 26 Name TRDY# DEVSEL# STOP# PERR# SERR# PAR Type I/O I/O I/O I/O O/D I/O Description Target device is ready to begin data transaction Device select. Indicates that a PCI target device address has been decoded PCI target device request to the PCI master to stop the current transaction Data parity error detected, driven by the device receiving data Address parity error Parity. Even parity computed for AD[31:0] and C/BE[3:0]; master drives PAR for address and write data phase, target drives PAR for read data phase
BootROM/EEPROM Interface 56~59 61~66 80~86 87 BrA0~3 BrA4~9 BrA10~15 BrA16/ LED M2 Fd/Col BrD0~4 BrD5/EDO BrD6/EDI BrD7/ECK EECS BrCS# BrOE# BrWE# I/O ROM data bus Provides up to 128kB EPROM or Flash-ROM application space. This pin can be programmed as mode 2 LED display for Full Duplex or Collision status. It will be driven (LED on) continually when a full duplex configuration is detected, or it will be driven at a 20 Hz blinking frequency when a collision status is detected in the half duplex configuration. O O/I O/O O/O O O O O BootROM data bus (0~7) EDO: Data output of serial EEPROM, data input to STE10/100 EDI:Data input to serial EEPROM, data output from STE10/100 ECK:Clock input to serial EEPROM, sourced by STE10/100 Chip Select of serial EEPROM BootROM Chip Select BootROM Read Output Enable for flash ROM application BootROM Write Enable for flash ROM application.
67~71 72 73 74 76 77 78 79
Physical Interface 98 X1 I 25 MHz reference clock input for Physical portion. When an external 25 MHz crystal is used, this pin will be connected to one of its terminals, and X2 will be connected to the other terminal. If an external 25 MHz oscillator is used, then this pin will be connected to the oscillator's output pin. 25 MHz reference clock output for Physical portion. When an external 25MHz crystal is used, this pin will be connected to one of the crystal terminals (see X1, above). If an external clock source is used, then this pin should be left open. The differential Transmit outputs of 100BASE-TX or 10BASE-T, these pins connect directly to Magnetic. The differential Receive inputs of 100BASE-TX or 10BASE-T, these pins connect directly from Magnetic. Reference Resistor connecting pin for reference current, directly connects a 5K Ohm 1% resistor to Vss.
97
X2
O
107,109 105,104 101
TX+, TXRX+, RXIref
O I O
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Table 1. Pin Description
Pin No. Name Type Description
LED display & Miscellaneous 90 LED M1LK/Act or LED M2Act O This pin can be programmed as mode 1 or mode 2: For mode 1: LED display for Link and Activity status. This pin will be driven on continually when a good Link test is detected. This pin will be driven at a 10 Hz blinking frequency when either effective receiving or transmitting is detected. For mode 2: LED display for Activity status. This pin will be driven at a 10 Hz blinking frequency when either effective receiving or transmitting is detected. This pin can be programmed as mode 1 or mode 2: For mode 1: LED display for 100M b/s or 10M b/s speed. This pin will be driven on continually when the 100M b/s network operating speed is detected. For mode 2: LED display for 100Ms/s link status. This pin will be driven on continually when 100Mb/s network operating spped is detected. This pin can be programmed as mode 1 or mode 2: For mode 1: LED display for Full Duplex or Collision status. This pin will be driven on continually when a full duplex configuration is detected. This pin will be driven at a 20 Hz blinking frequency when a collision status is detected in the half duplex configuration. For mode 2: LED display for 10Ms/s link status. This pin will be driven on continually when 10Mb/s network operating speed is detected. When this pin is asserted, it indicates an auxiliary power source is supported from the system. When this pin is asserted, it indicates a PCI power source is supported.
92
LED M1Speed or LED M2100 Link
O
91
LED M1Fd/Col or LED M210 Link
O
89 88
Vauxdetect Vcc-detect
I I
Digital Power Pins 5,11,19,31,36,39,45,51,55,75,93,112,115,125 8,14,27,38,40,48,60,85,111,122,128 Analog Power Pins 94,96,102,106,110 95,99,100,103,108 AVss AVdd Vss Vdd
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5.0 REGISTERS AND DESCRIPTORS DESCRIPTION
There are three kinds of registers within the STE10/100: STE10/100 configuration registers, PCI control/status registers, and Transceiver control/status registers. The STE10/100 configuration registers are used to initialize and configure the STE10/100 and for identifying and querying the STE10/100. The PCI control/status registers are used to communicate between the host and STE10/100. The host can initialize, control, and read the status of the STE10/100 through mapped I/O or memory address space.
The STE10/100 contains 11 16-bit registers to supported Transceiver control and status. They include 7 basic registers which are defined according to clause 22 "Reconciliation Sub-layer and Media Independent Interface" and clause 28 "Physical Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair" of the IEEE802.3u standard. In addition, 4 special registers are provided for advanced chip control and status. The STE10/100 also provides receive and transmit descriptors for packet buffering and management. 5.1 STE10/100 Configuration Registers An STE10/100 software driver can initialize and configure the chip by writing its configuration registers. The contents of configuration registers are set to their default values upon power-up or whenever a hardware reset occurs, but their settings remain unchanged whenever a software reset occurs. The configuration registers are byte, word, and double word accessible. Table 2. STE10/100 configuration registers list
Offset 00h 04h 08h 0ch 10h 14h 2ch 30h 34h 3ch 40h 80h c0h c4h Index CR0 CR1 CR2 CR3 CR4 CR5 CR11 CR12 CR13 CR15 CR16 CR32 CR48 CR49 Name LID CSC CC LT IOBA MBA SID BRBA CP CINT DS SIG PMR0 PMR1 Descriptions Loaded device ID and vendor ID Configuration Status and Command Class Code and revision number Latency Timer IO Base Address Memory Base Address Subsystem ID and vendor ID Boot ROM Base Address (ROM size = 128KB) Capability Pointer Configuration Interrupt driver space for special purpose Signature of STE10/100 Power Management Register 0 Power Management Register 1
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Table 3. STE10/100 configuration registers table
offset 00h 04h 08h 0ch 10h 14h 18h~ 28h 2ch 30h 34h 38h 3ch 40h 80h c0h c4h
Note:
b31
----------Device ID* Status
b16
b15
---------Vendor ID* Command
b0
Base Class Code ------
Subclass ------
-----Latency timer Base I/O address
Revision #
Step #
cache line size
Base memory address Reserved Subsystem ID* Boot ROM base address Reserved Reserved Max_Lat* Reserved Min_Gnt* Interrupt pin Driver Space Signature of STE10/100 PMC Reserved
* : automatically recalled from EEPROM when PCI reset is deserted DS(40h), bit15-8, is read/write able register SIG(80h) is hard wired register, read only
Subsystem vendor ID*
Cap_Ptr
Interrupt line Reserved
Next_Item_Ptr PMCSR
Cap_ID
5.1.1 STE10/100 configuration registers descriptions Table 4. Configuration Registers Descriptions
Bit # Name Descriptions Default Val RW Type
CR0(offset = 00h), LID - Loaded Identification number of Device and Vendor 31~16 15~0 LDID LVID Loaded Device ID, the device ID number loaded from serial EEPROM. Loaded Vendor ID, the vendor ID number loaded from serial EEPROM. From EEPROM From EEPROM R/O R/O
From EEPROM: Loaded from EEPROM
CR1(offset = 04h), CSC - Configuration command and status 31 SPE Status Parity Error. 1: means that STE10/100 detected a parity error. This bit will be set even if the parity error response (bit 6 of CR1) is disabled. Status System Error. 1: means that STE10/100 asserted the system error pin. 0 R/W
30
SES
0
R/W
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Table 4. Configuration Registers Descriptions
Bit # 29 Name SMA Descriptions Status Master Abort. 1: means that STE10/100 received a master abort and has terminated a master transaction. Status Target Abort. 1: means that STE10/100 received a target abort and has terminated a master transaction. Reserved. Status Device Select Timing. Indicates the timing of the chip's assertion of device select. 01: indicates a medium assertion of DEVSEL# Status Data Parity Report. 1: when three conditions are met: a. STE10/100 asserted parity error (PERR#) or it detected parity error asserted by another device. b. STE10/100 is operating as a bus master. c. STE10/100's parity error response bit (bit 6 of CR1) is enabled. Status Fast Back-to-Back Always 1, since STE10/100 has the ability to accept fast back to back transactions. Reserved. New Capabilities. Indicates whether the STE10/100 provides a list of extended capabilities, such as PCI power management. 1: the STE10/100 provides the PCI management function 0: the STE10/100 doesn't provide New Capabilities. Reserved. Command System Error Response 1: enable system error response. The STE10/100 will assert SERR# when it finds a parity error during the address phase. Reserved. Command Parity Error Response 0: disable parity error response. STE10/100 will ignore any detected parity error and keep on operating. Default value is 0. 1: enable parity error response. STE10/100 will assert system error (bit 13 of CSR5) when a parity error is detected. Reserved. Command Master Operation Ability 0: disable the STE10/100 bus master ability. 1: enable the PCI bus master ability. Default value is 1 for normal operation. Command Memory Space Access 0: disable the memory space access ability. 1: enable the memory space access ability. 0 R/W 0 R/W 0 R/W Same as bit 19 of CSR18 RO 01 R/O Default Val 0 RW Type R/W
28
STA
0
R/W
27 26, 25
--SDST
24
SDPR
0
R/W
23
SFBB
1
R/O
22~21 20
--NC
19~ 9 8
--CSE
7 6
--CPE
5~ 3 2
--CMO
1
CMSA
0
R/W
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Table 4. Configuration Registers Descriptions
Bit # 0 Name CIOSA Descriptions Command I/O Space Access 0: enable the I/O space access ability. 1: disable the I/O space access ability. Default Val 0 RW Type R/W
R/W: Read and Write able. RO: Read able only.
CR2(offset = 08h), CC - Class Code and Revision Number 31~24 23~16 15~ 8 7~4 3~0
RO: Read Only.
BCC SC --RN SN
Base Class Code. It means STE10/100 is a network controller. Subclass Code. It means STE10/100 is a Fast Ethernet Controller. Reserved. Revision Number, identifies the revision number of STE10/ 100. Step Number, identifies the STE10/100 steps within the current revision.
02h 00h
RO RO
Ah 1h
RO RO
CR3(offset = 0ch), LT - Latency Timer 31~16 15~ 8 --LT Reserved. Latency Timer. This value specifies the latency timer of the STE10/100 in units of PCI bus clock cycles. Once the STE10/100 asserts FRAME#, the latency timer starts to count. If the latency timer expires and the STE10/100 is still asserting FRAME#, the STE10/100 will terminate the data transaction as soon as its GNT# is removed. Cache Line Size. This value specifies the system cache line size in units of 32-bit double words(DW). The STE10/100 supports cache line sizes of 8, 16, or 32 DW. CLS is used by the STE10/100 driver to program the cache alignment bits (bit 14 and 15 of CSR0) which are used for cache oriented PCI commands, e.g., memory-read-line, memory-read-multiple, and memory-write-and-invalidate. 0 R/W
7~0
CLS
0
R/W
CR4(offset = 10h), IOBA - I/O Base Address 31~ 7 IOBA I/O Base Address. This value indicate the base address of PCI control and status register (CSR0~28), and Transceiver registers (XR0~10) reserved. I/O Space Indicator. 1: means that the configuration registers map into I/O space. 1 RO 0 R/W
6~1 0
--IOSI
CR5(offset = 14h), MBA - Memory Base Address 31~ 7 MBA Memory Base Address. This value indicate the base address of PCI control and status register(CSR0~28), and Transceiver registers(XR0~10) reserved. 0 R/W
6~1
---
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Table 4. Configuration Registers Descriptions
Bit # 0 Name IOSI Descriptions Memory Space Indicator. 1: means that the configuration registers map into I/O space. Default Val 0 RW Type RO
CR11(offset = 2ch), SID - Subsystem ID. 31~16 15~ 0 SID SVID Subsystem ID. This value is loaded from EEPROM as a result of power-on or hardware reset. Subsystem Vendor ID. This value is loaded from EEPROM as a result power-on or hardware reset. From EEPROM From EEPROM RO RO
CR12(offset = 30h), BRBA - Boot ROM Base Address. This register should be initialized before accessing the boot ROM space. 31~10 BRBA Boot ROM Base Address. This value indicates the address mapping of the boot ROM field as well as defining the boot ROM size. The values of bit 16~10 are set to 0 indicating that the STE10/100 supports up to 128kB of boot ROM. reserved Boot ROM Enable. The STE10/100 will only enable its boot ROM access if both the memory space access bit (bit 1 of CR1) and this bit are set to 1. 1: enable Boot ROM. (if bit 1 of CR1 is also set) 0 X: b31~17 0: b16~10 R/W RO
9~1 0
--BRE
RO R/W R/ W R/W
CR13(offset = 34h), CP - Capabilities Pointer. 31~8 7~0 --CP reserved Capabilities Pointer. C0H RO
CR15(offset = 3ch), CI - Configuration Interrupt 31~24 ML Max_Lat register. This value indicates how often the STE10/ 100 needs to access to the PCI bus in units of 250ns. This value is loaded from serial EEPROM as a result of power-on or hardware reset. Min_Gnt register. This value indicates how long the STE10/ 100 needs to retain the PCI bus ownership whenever it initiates a transaction, in units of 250ns. This value is loaded from serial EEPROM as a result power-on or hardware reset. Interrupt Pin. This value indicates one of four interrupt request pins to which the STE10/100 is connected. 01h: means the STE10/100 always connects to INTA# Interrupt Line. This value indicates the system interrupt request lines to which the INTA# of STE10/100 is routed. The BIOS will fill this field when it initializes and configures the system. The STE10/100 driver can use this value to determine priority and vector information. From EEPROM RO
23~16
MG
From EEPROM
RO
15~ 8
IP
01h
RO
7~0
IL
0
R/W
CR16(offset = 40h), DS - Driver Space for special purpose. 31~16 --reserved
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Table 4. Configuration Registers Descriptions
Bit # 15~8 Name DS Descriptions Driver Space for implementation-specific purpose. Since this area won't be cleared upon software reset, an STE10/100 driver can use this R/W area as user-specified storage. reserved Default Val 0 RW Type R/W
7~0
---
CR32(offset = 80h), SIG - Signature of STE10/100 31~16 15~0 DID VID Device ID, the device ID number of the STE10/100. Vendor ID 0981h 1317h RO RO
CR48(offset = c0h), PMR0, Power Management Register0. 31 30 29 28 27 PSD3c, PSD3h, PSD2, PSD1, PSD0 PME_Support. The STE10/100 will assert PME# signal while in the D0, D1, D2, D3hot and D3cold power state. The STE10/100 supports Wake-up from the above five states. Bit 31 (support wake-up from D3cold) is loaded from EEPROM after power-up or hardware reset. To support the D3cold wake-up function, an auxiliary power source will be sensed during reset by the STE10/100 Vaux_detect pin. If sensed low, PSD3c will be set to 0; if sensed high, and if D3CS (bit 31of CSR18) is set (CSR18 bits 16~31 are recalled from EEPROM at reset), then bit 31 will be set to 1. D2_Support. The STE10/100 supports the D2 Power Management State. D1_Support. The STE10/100 supports the D1 Power Management State. Aux Current. These three bits report the maximum 3.3Vaux current requirements for STE10/100 chip. If bit 31 of PMR0 is `1', the default value is 111b, meaning the STE10/100 needs 375 mA to support remote wake-up in D3cold power state. Otherwise, the default value is 000b, meaning the STE10/100 does not support remote wake-up from D3cold power state. The Device Specific Initialization bit indicates whether any special initialization of this function is required before the generic class device driver is able to use it. 0: indicates that the function does not require a device-specific initialization sequence following transition to the D0 uninitialized state. Reserved. PME Clock. Indicates that the STE10/100 does not rely on the presence of the PCI clock for PME# operation Version. The value of 010b indicates that the STE10/100 complies with Revision 1.0a of the PCI Power Management Interface Specification. Next Item Pointer. This value is always 0h, indicating that there are no additional items in the Capabilities List. Capability Identifier. This value is always 01h, indicating the link list item as being the PCI Power Management Registers. 0 010b RO RO X1111b RO
26 25 24~22
D2S D1S AUXC
1 1 XXXb
RO RO RO
21
DSI
0
RO
20 19 18~16
--PMEC VER
15~8 7~0
NIP CAPID
00h 01h
RO RO
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Table 4. Configuration Registers Descriptions
Bit # Name Descriptions Default Val RW Type
CR49(offset = c4h), PMR1, Power Management Register 1. 31~16 15 --PMEST reserved PME_Status. This bit is set whenever the STE10/100 detects a wake-up event, regardless of the state of the PME-En bit. Writing a "1" to this bit will clear it, causing the STE10/100 to deassert PME# (if so enabled). Writing a "0" has no effect. If PSD3c (bit 31 of PMR0) is cleared (i.e. it does not support PME# generation from D3cold), this bit is by default 0; otherwise, PMEST is cleared upon power-up reset only and is not modified by either hardware or software reset. Data_Scale. Indicates the scaling factor to be used when interpreting the value of the Data register. This field is required for any function that implements the Data register. The STE10/100 does not support Data register and Data_Scale. Data_Select. This four bit field is used to select which data is to be reported through the Data register and Data_Scale field. This field is required for any function that implements the Data register. The STE10/100 does not support Data_select. PME_En. When set, enables the STE10/100 to assert PME#. When cleared, disables the PME# assertion. If PSD3c (bit 31 of PMR0) is cleared (i.e. it does not support PME# generation from D3cold), this bit is by default 0; otherwise, PME_En is cleared upon power up reset only and is not modified by either hardware or software reset. reserved. PowerState. This two bit field is used both to determine the current power state of the STE10/100 and to place the STE10/ 100 in a new power state. The definition of this field is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot If software attempts to write an unsupported state to this field, the write operation will complete normally on the bus, but the data is discarded and no state change occurs. X R/W1C*
14,13
DSCAL
00b
RO
12~9
DSEL
0000b
R/W
8
PME_En
X
R/W
7~2 1,0
--PWRS
000000b 00b
RO R/W
R/W1C*, Read Only and Write one cleared.
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STE10/100
5.2 PCI Control/Status registers Table 5. PCI Control/Status registers list
offset from base address of CSR 00h 08h 10h 18h 20h 28h 30h 38h 40h 48h 50h 58h 60h 68h 70h 78h 80h 84h 88h 8ch 90h 94h 98h 9ch a0h a4h a8h ach b0h Index CSR0 CSR1 CSR2 CSR3 CSR4 CSR5 CSR6 CSR7 CSR8 CSR9 CSR10 CSR11 CSR12 CSR13 CSR14 CSR15 CSR16 CSR17 CSR18 CSR19 CSR20 CSR21 CSR22 CSR23 CSR24 CSR25 CSR26 CSR27 CSR28 Name PAR TDR RDR RDB TDB SR NAR IER LPC SPR --TMR --WCSR WPDR WTMR ACSR5 ACSR7 CR PCIC PMCSR ----TXBR FROM PAR0 PAR1 MAR0 MAR1 PCI access register transmit demand register receive demand register receive descriptor base address transmit descriptor base address status register network access register interrupt enable register lost packet counter serial port register Reserved Timer Reserved Wake-up Control/Status Register Wake-up Pattern Data Register watchdog timer status register 2 interrupt enable register 2 command register PCI bus performance counter Power Management Command and Status Reserved Reserved transmit burst counter/time-out register flash(boot) ROM port physical address register 0 physical address register 1 multicast address hash table register 0 multicast address hash table register 1 Descriptions
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STE10/100
Table 6. Control/Status register description
Bit # Name Descriptions Default Val RW Type
CSR0(offset = 00h), PAR - PCI Access Register 31~25 24 --MWIE reserved Memory Write and Invalidate Enable. 1: enable STE10/100 to generate memory write invalidate command. The STE10/100 will generate this command while writing full cache lines. 0: disable generating memory write invalidate command. The STE10/100 will use memory write commands instead. Memory Read Line Enable. 1: enable STE10/100 to generate memory read line command when read access instruction reaches the cache line boundary. If the read access instruction doesn't reach the cache line boundary then the STE10/100 uses the memory read command instead. reserved Memory Read Multiple Enable. 1: enable STE10/100 to generate memory read multiple commands when reading a full cache line. If the memory is not cache-aligned, the STE10/100 uses the memory read command instead. reserved Transmit auto-polling in transmit suspended state. 00: disable auto-polling (default) 01: polling own-bit every 200 us 10: polling own-bit every 800 us 11: polling own-bit every 1600 us reserved Cache alignment. Address boundary for data burst, set after reset 00: reserved (default) 01: 8 DW boundary alignment 10: 16 DW boundary alignment 11: 32 DW boundary alignment Programmable Burst Length. This value defines the maximum number of DW to be transferred in one DMA transaction. value: 0 (unlimited), 1, 2, 4, 8, 16(default), 32 Big or Little Endian selection. 0: little endian (e.g. INTEL) 1: big endian (only for data buffer) Descriptor Skip Length. Defines the gap between two descriptors in the units of DW. Bus arbitration 0: receive operations have higher priority 1: transmit operations have higher priority 00 R/W* 00 R/W* 0 R/W* 0 R/W*
23
MRLE
0
R/W*
22 21
--MRME
20~19 18,17
--TAP
16 15, 14
--CAL
13 ~ 8
PBL
010000
R/W*
7
BLE
0
R/W*
6~2 1
DSL BAR
0 0
R/W* R/W*
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STE10/100
Table 6. Control/Status register description
Bit # 0 Name SWR Descriptions Software reset 1: reset all internal hardware (including MAC and transceivers), except configuration registers. This signal will be cleared by the STE10/100 itself after the reset process is completed. Default Val 0 RW Type R/W*
R/W* = Before writing the transmit and receive operations should be stopped.
CSR1(offset = 08h), TDR - Transmit demand register 31~ 0 TPDM Transmit poll demand. While the STE10/100 is in the suspended state, a write to this register (any value) will trigger the read-tx-descriptor process, which checks the own-bit; if set, the transmit process is then started. FFFFFFFF h R/W*
R/W* = Before writing the transmit process should be in the suspended state.
CSR2(offset = 10h), RDR - Receive demand register 31 ~ 0 RPDM Receive poll demand While the STE10/100 is in the suspended state, a write to this register (any value) will trigger the read-rx-descriptor process, which checks the own-bit, if set, the process to move data from the FIFO to buffer is then started. FFFFFFFF h R/W*
R/W* = Before writing the receive process should be in the suspended state.
CSR3(offset = 18h), RDB - Receive descriptor base address 31~ 2 1, 0 SAR RBND Start address of receive descriptor must be 00, DW boundary 0 00 R/W* RO
R/W* = Before writing the receive process should be stopped.
CSR4(offset = 20h), TDB - Transmit descriptor base address 31~ 2 1, 0 SAT TBND Start address of transmit descriptor must be 00, DW boundary 0 00 R/W* RO
R/W* = Before writing the transmit process should be stopped.
CSR5(offset = 28h), SR - Status register 31~ 26 25~ 23 ---BET reserved Bus Error Type. This field is valid only when bit 13 of CSR5(fatal bus error) is set. There is no interrupt generated by this field. 000: parity error, 001: master abort, 010: target abort 011, 1xx: reserved 000 RO
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STE10/100
Table 6. Control/Status register description
Bit # 22~ 20 Name TS Descriptions Transmit State. Reports the current transmission state only, no interrupt will be generated. 000: stop 001: read descriptor 010: transmitting 011: FIFO fill, read the data from memory and put into FIFO 100: reserved 101: reserved 110: suspended, unavailable transmit descriptor or FIFO overflow 111: write descriptor Receive State. Reports current receive state only, no interrupt will be generated. 000: stop 001: read descriptor 010: check this packet and pre-fetch next descriptor 011: wait for receiving data 100: suspended 101: write descriptor 110: flush the current FIFO 111: FIFO drain, move data from receiving FIFO into memory Normal Interrupt Status Summary. Set if any of the following bits of CSR5 are asserted: TCI, transmit completed interrupt (bit 0) TDU, transmit descriptor unavailable (bit 2) RCI, receive completed interrupt (bit 6) Abnormal Interrupt Status Summary. Set if any of the following bits of CSR5 are asserted: TPS, transmit process stopped (bit 1) TJT, transmit jabber timer time-out (bit 3) TUF, transmit under-flow (bit 5) RDU, receive descriptor unavailable (bit 7) RPS, receive process stopped (bit 8) RWT, receive watchdog time-out (bit 9) GPTT, general purpose timer time-out (bit 11) FBE, fatal bus error (bit 13) reserved Fatal Bus Error. 1: on occurrence of parity error, master abort, or target abort (see bits 25~23 of CSR5). The STE10/100 will disable all bus access. A software reset is required to recover from a parity error. reserved General Purpose Timer Timeout, based on CSR11 timer register reserved Receive Watchdog Timeout, based on CSR15 watchdog timer register Receive Process Stopped, receive state = stop 0 0 RO/LH* RO/LH* 0 RO/LH* 0 RO/LH* Default Val 000 RW Type RO
19~17
RS
000
RO
16
NISS
0
RO/LH*
15
AISS
0
RO/LH*
14 13
---FBE
12 11 10 9 8
--GPTT --RWT RPS
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STE10/100
Table 6. Control/Status register description
Bit # 7 Name RDU Descriptions Receive Descriptor Unavailable 1: when the next receive descriptor can not be obtained by the STE10/100. The receive process is suspended in this situation. To restart the receive process, the ownership bit of the next receive descriptor should be set to STE10/100 and a receive poll demand command should be issued (if the receive poll demand is not issued, the receive process will resume when a new recognized frame is received). Receive Completed Interrupt 1: when a frame reception is completed. Transmit Under-Flow 1: when an under-flow condition occurs in the transmit FIFO during transmitting. The transmit process will enter the suspended state and report the under-flow errror on bit 1 of TDES0. Reserved Transmit Jabber Timer Time-out 1: when the transmit jabber timer expires. The transmit processor will enter the stop state and TO (bit 14 of TDES0, transmit jabber time-out flag) will be asserted. Transmit Descriptor Unavailable 1: when the next transmit descriptor can not be obtained by the STE10/100. The transmission process is suspended in this situation. To restart the transmission process, the ownership bit of the next transmit descriptor should be set to STE10/100 and, if the transmit automatic polling is not enabled, a transmit poll demand command should then be issued. Transmit Process Stopped. 1: while transmit state = stop Transmit Completed Interrupt. 1: set when a frame transmission completes with IC (bit 31 of TDES1) asserted in the first transmit descriptor of the frame. 0 RO/LH* Default Val 0 RW Type RO/LH*
6 5
RCI TUF
0 0
RO/LH* RO/LH*
4 3
--TJT
2
TDU
0
RO/LH*
1 0
TPS TCI
0 0
RO/LH* RO/LH*
LH = High Latching and cleared by writing 1.
CSR6(offset = 30h), NAR - Network access register 31~22 21 --SF reserved Store and forward for transmit 0: disable 1: enable, ignore the transmit threshold setting reserved SQE Disable 0: enable SQE function for 10BASE-T operation. The STE10/ 100 provides SQE test function for 10BASE-T half duplex operation. 1: disable SQE function. reserved 1 R/W* 0 R/W*
20 19
--SQE
18~16
-----
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STE10/100
Table 6. Control/Status register description
Bit # 15~14 Name TR Descriptions transmit threshold control 00: 128-bytes (100Mbps), 72-bytes (10Mbps) 01: 256-bytes (100Mbps), 96-bytes (10Mbps) 10: 512-bytes (100Mbps), 128-bytes (10Mbps) 11: 1024-bytes (100Mbps), 160-bytes (10Mbps) Stop transmit 0: stop (default) 1: start Force collision mode 0: disable 1: generate collision upon transmit (for testing in loop-back mode) Operating Mode 00: normal 01: MAC loop-back, regardless of contents of XLBEN (bit 14 of XR0, XCVR loop-back) 10,11: reserved reserved Multicast Mode 1: receive all multicast packets Promiscuous Mode 1: receive any good packet. 0: receive only the right destination address packets Stop Back-off Counter 1: back-off counter stops when carrier is active, and resumes when carrier is dropped. 0: back-off counter is not effected by carrier reserved Pass Bad packet 1: receives any packets passing address filter, including runt packets, CRC error, truncated packets. For receiving all bad packets, PR (bit 6 of CSR6) should be set to 1. 0: filters all bad packets reserved Start/Stop Receive 0: receive processor will enter stop state after the current frame reception is completed. This value is effective only when the receive processor is in the running or suspending state. Note: In "Stop Receive" state, the PAUSE packet and Remote Wake Up packet will not be affected and can be received if the corresponding function is enabled. 1: receive processor will enter running state. reserved 0 R/W 0 R/W*** 0 1 R/W*** R/W*** Default Val 00 RW Type R/W*
13
ST
0
R/W
12
FC
0
R/W**
11, 10
OM
00
R/W**
9, 8 7 6
--MM PR
5
SBC
0
R/W**
4 3
--PB
2 1
--SR
0
---
W* = only write when the transmit processor stopped. W** = only write when the transmit and receive processor both stopped. W*** = only write when the receive processor stopped.
CSR7(offset = 38h), IER - Interrupt Enable Register
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STE10/100
Table 6. Control/Status register description
Bit # 31~17 16 15 14 13 Name --NIE AIE --FBEIE reserved Normal Interrupt Enable 1: enables all the normal interrupt bits (see bit 16 of CSR5) Abnormal Interrupt Enable 1: enables all the abnormal interrupt bits (see bit 15 of CSR5) reserved Fatal Bus Error Interrupt Enable 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the fatal bus error interrupt Reserved General Purpose Timer Interrupt Enable 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the general purpose timer expired interrupt. Reserved Receive Watchdog Time-out Interrupt Enable 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the receive watchdog time-out interrupt. Receive Stopped Interrupt Enable 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the receive stopped interrupt. Receive Descriptor Unavailable Interrupt Enable 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the receive descriptor unavailable interrupt. Receive Completed Interrupt Enable 1: this bit in conjunction with NIE (bit 16 of CSR7) will enable the receive completed interrupt. Transmit Under-flow Interrupt Enable 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the transmit under-flow interrupt. Reserved Transmit Jabber Timer Time-out Interrupt Enable 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the transmit jabber timer time-out interrupt. Transmit Descriptor Unavailable Interrupt Enable 1: this bit in conjunction with NIE (bit 16 of CSR7) will enable the transmit descriptor unavailable interrupt. Transmit Processor Stopped Interrupt Enable 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the transmit processor stopped interrupt. Transmit Completed Interrupt Enable 1: this bit in conjunction with NIE (bit 16 of CSR7) will enable the transmit completed interrupt. 0 R/W 0 R/W 0 R/W 0 R/W 0 0 R/W R/W Descriptions Default Val RW Type
12 11
--GPTIE
10 9
--RWTIE
8
RSIE
0
R/W
7
RUIE
0
R/W
6
RCIE
0
R/W
5
TUIE
0
R/W
4 3
--TJTTIE
2
TDUIE
0
R/W
1
TPSIE
0
R/W
0
TCIE
0
R/W
CSR8(offset = 40h), LPC - Lost packet counter
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STE10/100
Table 6. Control/Status register description
Bit # 31~17 16 Name --LPCO Reserved Lost Packet Counter Overflow 1: when lost packet counter overflow occurs. Cleared after read. Lost Packet Counter The counter is incremented whenever a packet is discarded as a result of no host receive descriptors being available. Cleared after read. 0 RO/LH Descriptions Default Val RW Type
15~0
LPC
0
RO/LH
CSR9(offset = 48h), SPR - Serial port register 31~15 14 --SRC Reserved Serial EEPROM Read Control When set, enables read access from EEPROM, when SRS (CSR9 bit 11) is also set. Serial EEPROM Write Control When set, enables write access to EEPROM, when SRS (CSR9 bit 11) is also set. Reserved Serial EEPROM Select When set, enables access to the serial EEPROM (see description of CSR9 bit 14 and CSR9 bit 13) Reserved Serial EEPROM data out This bit serially shifts data from the EEPROM to the STE10/ 100. Serial EEPROM data in This bit serially shifts data from the STE10/100 to the EEPROM. Serial EEPROM clock High/Low this bit to provide the clock signal for EEPROM. Serial EEPROM chip select 1: selects the serial EEPROM chip. 1 RO 0 R/W 0 R/W
13
SWC
0
R/W
12 11
--SRS
10~4 3
--SDO
2
SDI
1
R/W
1 0
SCLK SCS
1 1
R/W R/W
CSR11(offset = 58h), TMR -General-purpose Timer 31~17 16 --COM Reserved Continuous Operation Mode 1: sets the general-purpose timer in continuous operating mode. General-purpose Timer Value Sets the counter value. This is a count-down counter with a cycle time of 204us. 0 R/W
15~0
GTV
0
R/W
CSR13(offset = 68h), WCSR -Wake-up Control/Status Register 31 --Reserved
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STE10/100
Table 6. Control/Status register description
Bit # 30 Name CRCT Descriptions CRC-16 Type 0: Initial contents = 0000h 1: Initial contents = FFFFh Wake-up Pattern One Matched Enable. Wake-up Pattern Two Matched Enable. Wake-up Pattern Three Matched Enable. Wake-up Pattern Four Matched Enable. Wake-up Pattern Five Matched Enable. Reserved Link Off Detect Enable. The STE10/100 will set the LSC bit of CSR13 after it has detected that link status has transitioned from ON to OFF. Link On Detect Enable. The STE10/100 will set the LSC bit of CSR13 after it has detected that link status has transitioned from OFF to ON. Reserved Wake-up Frame Received Enable. The STE10/100 will include the "Wake-up Frame Received" event in its set of wake-up events. If this bit is set, STE10/100 will assert PMEST bit of PMR1 (CR49) after STE10/100 has received a matched wake-up frame. Magic Packet Received Enable. The STE10/100 will include the "Magic Packet Received" event in its set of wake-up events. If this bit is set, STE10/100 will assert PMEST bit of PMR1 (CR49) after STE10/100 has received a Magic packet. Link Status Changed Enable. The STE10/100 will include the "Link Status Changed" event in its set of wake-up events. If this bit is set, STE10/100 will assert PMEST bit of PMR1 after STE10/100 has detected a link status changed event. Reserved Wake-up Frame Received, 1: Indicates STE10/100 has received a wake-up frame. It is cleared by writing a 1 or upon power-up reset. It is not affected by a hardware or software reset. Magic Packet Received, 1: Indicates STE10/100 has received a magic packet. It is cleared by writing a 1 or upon power-up reset. It is not affected by a hardware or software reset. Link Status Changed, 1: Indicates STE10/100 has detected a link status change event. It is cleared by writing a 1 or upon power-up reset. It is not affected by a hardware or software reset. X R/W1C* 0 R/W 0 R/W Default Val 0 RW Type R/W
29 28 27 26 25 24-18 17
WP1E WP2E WP3E WP4E WP5E --LinkOFF
0 0 0 0 0
R/W R/W R/W R/W R/W
16
LinkON
0
R/W
15-11 10
--WFRE
9
MPRE
Default 1 if PM & WOL bits of CSR 18 are both enabled. 0
R/W
8
LSCE
R/W
7-3 2
--WFR
1
MPR
X
R/W1C*
0
LSC
X
R/W1C*
R/W1C*, Read Only and Write one cleared.
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STE10/100
Table 6. Control/Status register description
CSR14(offset = 70h), WPDR -Wake-up Pattern Data Register Offset 0000h 0004h 0008h 000ch 0010h 0014h 0018h 001ch 0020h 0024h 0028h 002ch 0030h 0034h 0038h 003ch 0040h 0044h 0048h 004ch 0050h 0054h 0058h 005ch 0060h 31 16 15 8 7 0
Wake-up pattern 1 mask bits 31:0 Wake-up pattern 1 mask bits 63:32 Wake-up pattern 1 mask bits 95:64 Wake-up pattern 1 mask bits 127:96 CRC16 of pattern 1 Reserved Wake-up pattern 2 mask bits 31:0 Wake-up pattern 2 mask bits 63:32 Wake-up pattern 2 mask bits 95:64 Wake-up pattern 2 mask bits 127:96 CRC16 of pattern 2 Reserved Wake-up pattern 3 mask bits 31:0 Wake-up pattern 3 mask bits 63:32 Wake-up pattern 3 mask bits 95:64 Wake-up pattern 3 mask bits 127:96 CRC16 of pattern 3 Reserved Wake-up pattern 4 mask bits 31:0 Wake-up pattern 4 mask bits 63:32 Wake-up pattern 4 mask bits 95:64 Wake-up pattern 4 mask bits 127:96 CRC16 of pattern 4 Reserved Wake-up pattern 5 mask bits 31:0 Wake-up pattern 5 mask bits 63:32 Wake-up pattern 5 mask bits 95:64 Wake-up pattern 5 mask bits 127:96 CRC16 of pattern 5 Reserved Wake-up pattern 5 offset Wake-up pattern 4 offset Wake-up pattern 3 offset Wake-up pattern 2 offset Wake-up pattern 1 offset
1. Offset value is from 0-255 (8-bit width). 2. To load the whole wake-up frame filtering information, consecutive 25 long words write operation to CSR14 should be done.
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STE10/100
Table 6. Control/Status register description
Bit # Name Descriptions Default Val RW Type
CSR15(offset = 78h), WTMR - Watchdog timer 31~6 5 --RWR Reserved Receive Watchdog Release. The time (in bit-times) from sensing dropped carrier to releasing watchdog timer. 0: 24 bit-times 1: 48 bit-times Receive Watchdog Disable 0: If the received packet`s length exceeds 2560 bytes, the watchdog timer will expire. 1: disable the receive watchdog. Reserved Jabber clock 0: cut off transmission after 2.6 ms (100Mbps) or 26 ms (10Mbps). 1: cut off transmission after 2560 byte-time. Non-Jabber 0: if jabber expires, re-enable transmit function after 42 ms (100Mbps) or 420ms (10Mbps). 1: immediately re-enable the transmit function after jabber expires. Jabber disable 1: disable transmit jabber function 0 R/W 0 R/W
4
RWD
0
R/W
3 2
--JCLK
1
NJ
0
R/W
0
JBD
0
R/W
CSR16(offset = 80h), ACSR5 - Assistant CSR5(Status register 2) 31 TEIS Transmit Early Interrupt status Transmit early interrupt status is set to 1 when TEIE (bit 31 of CSR17 set) is enabled and the transmitted packet is moved from descriptors to the TX-FIFO buffer. This bit is cleared by writing a 1. Receive Early Interrupt Status. Receive early interrupt status is set to 1 when REIE (CSR17 bit 30) is enabled and the received packet has filled up its first receive descriptor. This bit is cleared by writing a 1. Transceiver (XCVR) Interrupt Status. Formed by the logical OR of XR8 bits 6~0. Transmit Deferred Interrupt Status. Reserved PAUSE Frame Received Interrupt Status 1: indicates receipt of a PAUSE frame while the PAUSE function is enabled. Bus Error Type. This field is valid only when FBE (CSR5 bit 13, fatal bus error) is set. There is no interrupt generated by this field. 000: parity error, 001: master abort, 010: target abort 011, 1xx: reserved 0 RO/LH* 0 RO/LH*
30
REIS
0
RO/LH*
29 28 27 26
XIS TDIS --PFR
0 0
RO/LH* RO/LH*
25~ 23
BET
000
RO
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STE10/100
Table 6. Control/Status register description
Bit # 22~ 20 Name TS Descriptions Transmit State. Reports the current transmission state only, no interrupt will be generated. 000: stop 001: read descriptor 010: transmitting 011: FIFO fill, read the data from memory and put into FIFO 100: reserved 101: reserved 110: suspended, unavailable transmit descriptor or FIFO overflow 111: write descriptor Receive State. Reports current receive state only, no interrupt will be generated. 000: stop 001: read descriptor 010: check this packet and pre-fetch next descriptor 011: wait for receiving data 100: suspended 101: write descriptor 110: flush the current FIFO 111: FIFO drain, move data from receiving FIFO into memory Added normal interrupt status summary. 1: whenever any of the added normal interrupts occur. Added Abnormal Interrupt Status Summary. 1: whenever any of the added abnormal interrupts occur. These bits are the same as the status register of CSR5, and are accessible through either CSR5 or CSR16. Default Val 000 RW Type RO
19~17
RS
000
RO
16 15 14~0
ANISS AAISS
0 0
RO/LH* RO/LH*
LH* = High Latching and cleared by writing 1.
CSR17(offset = 84h), ACSR7- Assistant CSR7(Interrupt enable register 2) 31 30 29 28 27 26 25~17 16 TEIE REIE XIE TDIE --PFRIE --ANISE Transmit Early Interrupt Enable Receive Early Interrupt Enable Transceiver (XCVR) Interrupt Enable Transmit Deferred Interrupt Enable Reserved PAUSE Frame Received Interrupt Enable Reserved Added Normal Interrupt Summary Enable. 1: adds the interrupts of bits 30 and 31 of ACSR7 (CSR17) to the normal interrupt summary (bit 16 of CSR5). Added Abnormal Interrupt Summary Enable. 1: adds the interrupt of bits 27, 28, and 29 of ACSR7 (CSR17) to the abnormal interrupt summary (bit 16 of CSR5). These bits are the same as the interrupt enable register of CSR7, and are accessible through either CSR7 or CSR16. 0 R/W 0 R/W 0 0 0 0 R/W R/W R/W R/W
15
AAIE
0
R/W
14~0
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STE10/100
Table 6. Control/Status register description
Bit # Name Descriptions Default Val RW Type
CSR18(offset = 88h), CR - Command Register, bit31 to bit16 automatically recall from EEPROM 31 D3CS D3cold power state wake up Support. If this bit is reset then bit 31 of PMR0 will be reset to `0'. If this bit is asserted and an auxiliary power source is detected then bit 31 of PMR0 will be set to `1'. Aux. Current Load. These three bits report the maximum 3.3Vaux current requirements for STE10/100 chip. If bit 31 of PMR0 is `1', the default value is 111b, which means the STE10/100 need 375 mA to support remote wake-up in D3cold power state. Otherwise, the default value is 000b, which means the STE10/100 does not support remote wakeup from D3cold power state. Reserved 0 from EEPROM R/W 0 from EEPROM 000b from EEPROM R/W
30-28
AUXCL
R/W
27-24 23
---
4LEDmode This bit is used to control the LED mode selection. _on If this bit is reset, mode 1 (3 LEDs) is selected; the LEDs definition is: 100/10 speed Link/Activity Full Duplex/Collision If this bit is set, mode 2 (4 LEDs) is selected; the LEDs definition is: 100 Link 10 Link Activity Full Duplex/Collision RFS Receive FIFO size control 11: 1K bytes 10: 2K bytes 01,00: reserved Reserved Power Management. Enables the STE10/100 Power Management abilities. When this bit is set into "0" the STE10/ 100 will set the Cap_Ptr register to zero, indicating no PCI compliant power management capabilities. The value of this bit will be mapped to NC (CR1 bit 20). In PCI Power Management mode, the Wake Up Frames include "Magic Packet", "Unicast", and "Muliticast". Wake on LAN mode enable. When this bit is set to `1', then the STE10/100 enters Wake On LAN mode and enters the sleep state. Once the STE10/100 enters the sleep state, it remains there until: the Wake Up event occurs, the WOL bit is cleared, or a reset (software or hardware) happens. In Wake On LAN mode the Wake-Up frame is "Magic Packet" only. Reserved Reset Wake-up Pattern Data Register Pointer
22, 21
10 from EEPROM
R/W
20 19
--PM
X from EEPROM
RO
18
WOL
X from EEPROM
R/W
17~7 6
--RWP
0
R/W
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STE10/100
Table 6. Control/Status register description
Bit # 5 Name PAUSE Descriptions Disable or enable the PAUSE function for flow control. The default value of PAUSE is determined by the result of AutoNegotiation. The driver software can overwrite this bit to enable or disable it after the Auto-Negotiation has completed. 0: PAUSE function is disabled. 1: PAUSE function is enabled Receive Threshold Enable. 1: the receive FIFO threshold is enabled. 0: disable the receive FIFO threshold selection in DRT (bits 3~2), and the receive threshold is set to the default 64 bytes. Drain Receive Threshold 00: 32 bytes (8 DW) 01: 64 bytes (16 DW) 10: store-and -forward 11: reserved Software interrupt. 1: enable automatically transmit-underrun recovery. Default Val Depends on the result of AutoNegotiation 0 RW Type R/W
4
RTE
R/W
3~2
DRT
01
R/W
1 0
SINT ATUR
0 0
R/W R/W
CSR19(offset = 8ch) - PCIC, PCI bus performance counter 31~16 CLKCNT The number of PCI clocks from read request asserted to access completed. This PCI clock count is accumulated for all the read command cycles from the last CSR19 read to the current CSR19 read. reserved The number of double words accessed by the last bus master. This double word count is accumulated for all bus master data transactions from the last CSR19 read to the current CSR19 read. 0 RO* 0 RO*
15~8 7~0
--DWCNT
RO* = Read only and cleared by reading.
CSR20 (offset = 90h) - PMCSR, Power Management Command and Status (The same register value mapping to CR49-PMR1.) 31~16 15 --PMES reserved PME_Status. This bit is set whenever the STE10/100 detects a wake-up event, regardless of the state of the PME-En bit. Writing a "1" to this bit will clear it, causing the STE10/100 to deassert PME# (if so enabled). Writing a "0" has no effect. Data_Scale. Indicates the scaling factor to be used when interpreting the value of the Data register. This field is required for any function that implements the Data register. The STE10/100 does not support Data register and Data_Scale. Data_Select. This four bit field is used to select which data is to be reported through the Data register and Data_Scale field. This field is required for any function that implements the Data register. The STE10/100 does not support Data_select. 0 RO
14,13
DSCAL
00b
RO
12~9
DSEL
0000b
RO
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STE10/100
Table 6. Control/Status register description
Bit # 8 7~2 1,0 Name PME_En --PWRS Descriptions PME_En. When set, enables the STE10/100 to assert PME#. When cleared, disables the PME# assertion. reserved. PowerState, This two-bit field is used both to determine the current power state of the STE10/100 and to set the STE10/ 100 into a new power state. The definition of this field is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot If software attempts to write an unsupported state to this field, the write operation will complete normally on the bus, but the data is discarded and no state change occurs. Default Val 0 000000b 00b RW Type RO RO RO
CSR23(offset = 9ch) - TXBR, transmit burst count / time-out 31~21 20~16 --TBCNT reserved Transmit Burst Count Specifies the number of consecutive successful transmit burst writes to complete before the transmit completed interrupt will be generated. Transmit Time-Out = (deferred time + back-off time). When TDIE (ACSR7 bit 28) is set, the timer is decreased in increments of 2.56us (@100M) or 25.6us (@10M). If the timer expires before another packet transmit begins, then the TDIE interrupt will be generated. 0 R/W
11~0
TTO
0
R/W
CSR24(offset = a0h) - FROM, Flash ROM(also the boot ROM) port 31 bra16_on This bit is only valid when 4 LEDmode_on (CSR18 bit 23) is set. In this case, when bra16_on is set, pin 87 functions as brA16; otherwise it functions as LED pin - fd/col. reserved Read Enable. Clear if read data is ready in DATA, bit7-0 of FROM. Write Enable. Cleared if write completed. reserved Flash ROM address Read/Write data of flash ROM 0 0 R/W R/W 0 0 R/W R/W 1 R/W
30~28 27 26 25 24~8 7~0
--REN WEN --ADDR DATA
CSR25(offset = a4h) - PAR0, physical address register 0, automatically recalled from EEPROM 31~24 23~16 15~8 PAB3 PAB2 PAB1 physical address byte 3 physical address byte 2 physical address byte 1 From EEPROM From EEPROM From EEPROM R/W R/W R/W
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Table 6. Control/Status register description
Bit # 7~0 Name PAB0 physical address byte 0 Descriptions Default Val From EEPROM RW Type R/W
CSR26(offset = a8h) - PAR1, physical address register 1, automatically recalled from EEPROM 31~24 23~16 15~8 7~0 ----PAB5 PAB4 reserved reserved physical address byte 5 physical address byte 4 From EEPROM From EEPROM R/W R/W
For example, physical address = 00-00-e8-11-22-33 PAR0= 11 e8 00 00 PAR1= XX XX 33 22 PAR0 and PAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bits 19-17=000).
CSR27(offset = ach) - MAR0, multicast address register 0 31~24 23~16 15~8 7~0 MAB3 MAB2 MAB1 MAB0 multicast address byte 3 (hash table 31:24) multicast address byte 2 (hash table 23:16) multicast address byte 1 (hash table 15:8) multicast address byte 0 (hash table 7:0) 00h 00h 00h 00h R/W R/W R/W R/W
CSR28(offset = b0h) - MAR1, multicast address register 1 31~24 23~16 15~8 7~0 MAB7 MAB6 MAB5 MAB4 multicast address byte 7 (hash table 63:56) multicast address byte 6 (hash table 55:48) multicast address byte 5 (hash table 47:40) multicast address byte 4 (hash table 39:32) 00h 00h 00h 00h R/W R/W R/W R/W
MAR0 and MAR1 are readable, but can be written only if the receive state is in stopped(CSR5 bit19-17=000).
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5.3 Transceiver(XCVR) Registers There are 11 16-bit registers supporting the transceiver portion of STE10/100, including 7 basic registers defined according to clause 22 "Reconciliation Sublayer and Media Independent Interface" and clause 28 "Physical Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair" of the IEEE802.3u standard. In addition, 4 special registers are provided for advanced chip control and status.
Note: 1. Since only Double Word access is supported for Register R/W in the STE10/100, the higher word(bit 31~16) of the XCVR registers (XR0~XR10) should be ignored.
Table 7. Transceiver registers list
Offset from base address of CSR b4h b8h bch c0h c4h c8h cch d0h d4h d8h dch Reg. Index Name Register Descriptions
XR0 XR1 XR2 XR3 XR4 XR5 XR6 XR7 XR8 XR9 XR10
XCR XSR PID1 PID2 ANA ANLPA ANE XMC XCIIS XIE 100CTR
XCVR Control Register XCVR Status Register PHY Identifier 1 PHY Identifier 2 Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register XCVR Mode Control Register XCVR Configuration Information and Interrupt Status Register XCVR Interrupt Enable Register 100BASE-TX PHY Control/Status Register
Table 8. Transceiver registers Descriptions
Bit # Name Descriptions Default Val RW Type
XR0(offset = b4h) - XCR, XCVR Control Register. The default value is chosen as listed below. 15 XRST Transceiver Reset control. 1: reset transceiver. This bit will be cleared by STE10/100 after transceiver reset has completed. Transceiver loop-back mode select. 1: transceiver loop-back mode is selected. OM (CSR6 bits 11,10) of must contain 00. Network Speed select. This bit will be ignored if AutoNegotiation is enabled (ANEN, XR0 bit 12). 1:100Mbps is selected. 0:10Mbps is selected. Auto-Negotiation ability control. 1: Auto-Negotiation function is enabled. 0: Auto-Negotiation is disabled. 0 R/W
14
XLBEN
0
R/W
13
SPSEL
1
R/W
12
ANEN
1
R/W
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Table 8. Transceiver registers Descriptions
Bit # 11 Name PDEN Descriptions Power down mode control. 1: transceiver power-down mode is selected. In this mode, the STE10/100 transceivers are turned off. reserved Re-Start Auto-Negotiation process control. 1: Auto-negotiation process will be restarted. This bit will be cleared by STE10/100 after the Auto-negotiation has restarted. Full/Half duplex mode select. 1: full duplex mode is selected. This bit will be ignored if AutoNegotiation is enabled (ANEN, XR0 bit 12). Collision test control. 1: collision test is enabled. reserved Default Val 0 RW Type R/W
10 9
--RSAN
0 0
RO R/W
8
DPSEL
0
R/W
7 6~0
COLEN ---
0 0
R/W RO
R/W = Read/Write able. RO = Read Only.
XR1(offset = b8h) - XSR, XCVR Status Register. All the bits of this register are read only. 15 14 T4 TXFD 100BASE-T4 ability. Always 0, since STE10/100 has no T4 ability. 100BASE-TX full duplex ability. Always 1, since STE10/100 has 100BASE-TX full duplex ability. 100BASE-TX half duplex ability. Always 1, since STE10/100 has 100BASE-TX half duplex ability. 10BASE-T full duplex ability. Always 1, since STE10/100 has 10Base-T full duplex ability. 10BASE-T half duplex ability. Always 1, since STE10/100 has 10Base-T half duplex ability. reserved Auto-Negotiation Completed. 0: Auto-Negotiation process incomplete. 1: Auto-Negotiation process complete. Result of remote fault detection. 0: no remote fault condition detected. 1: remote fault condition detected. Auto-Negotiation ability. Always 1, since STE10/100 has Auto-negotiation ability. Link status. 0: a link failure condition occurred. Readin clears this bit. 1: valid link established. Jabber detection. 1: jabber condition detected (10Base-T only). 0 1 RO RO
13
TXHD
1
RO
12 11 10~6 5
10FD 10HD --ANC
1 1 0 0
RO RO RO RO
4
RF
0
RO/LH*
3 2
AN LINK
1 0
RO RO/LL*
1
JAB
0
RO/LH*
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Table 8. Transceiver registers Descriptions
Bit # 0 Name EXT Descriptions Extended register support. Always 1, since STE10/100 supports extended register Default Val 1 RW Type RO
LL* = Latching Low and clear by read. LH* = Latching High and clear by read.
XR2(offset = bch) - PID1, PHY identifier 1 15~0 PHYID1 Part one of PHY Identifier. Assigned to the 3 rd to 18th bits of the Organizationally Unique Identifier. 0382h RO
XR3(offset = c0h) - PID2, PHY identifier 2 15~10 PHYID2 Part two of PHY Identifier. Assigned to the 19th to 24th bits of the Organizationally Unique Identifier (OUI). Model number of STE10/100. 6-bit manufacturer's model number. Revision number of STE10/100. 4-bits manufacturer's revision number. 010010b RO
9~4 3~0
MODEL REV
000001b 0000b
RO RO
XR4(offset = c4h) - ANA, Auto-Negotiation Advertisement 15 14 13 12,11 10 9 8 7 6 5 4~0 NXTPG --RF --FC T4 TXF TXH 10F 10H SF Next Page ability. Always 0; STE10/100 does not provide next page ability. reserved Remote Fault function. 1: remote fault function present reserved Flow Control function Ability. 1: supports PAUSE operation of flow control for full duplex link. 100BASE-T4 Ability. Always 0; STE10/100 does not provide 100BASE-T4 ability. 100BASE-TX Full duplex Ability. 1: 100Base-TX full duplex ability supported 100BASE-TX Half duplex Ability. 1: 100Base-TX ability supported. 10BASE-T Full duplex Ability. 1: 10Base-T full duplex ability supported. 10BASE-T Half duplex Ability. 1: 10Base-T ability supported. Select field. Default 00001=IEEE 802.3 1 0 1 1 1 1 00001 R/W RO R/W R/W R/W R/W RO 0 R/W 0 RO
XR5(offset = c8h) - ANLP, Auto-Negotiation Link Partner ability 15 LPNP Link partner Next Page ability. 0: link partner without next page ability. 1: link partner with next page ability. 0 RO
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Table 8. Transceiver registers Descriptions
Bit # 14 Name LPACK Descriptions Received Link Partner Acknowledge. 0: link code word not yet received. 1: link partner successfully received STE10/100's link code word. Link Partner's Remote fault status. 0: no remote fault detected. 1: remote fault detected. reserved Link Partner's Flow control ability. 0: link partner without PAUSE function ability. 1, link partner with PAUSE function ability for full duplex link. Link Partner's 100BASE-T4 ability. 0: link partner without 100BASE-T4 ability. 1: link partner with 100BASE-T4 ability. Link Partner's 100BASE-TX Full duplex ability. 0: link partner without 100BASE-TX full duplex ability. 1: link partner with 100BASE-TX full duplex ability. Link Partner's 100BASE-TX Half duplex ability. 0: link partner without 100BASE-TX. 1: link partner with 100BASE-TX ability. Link Partner's 10BASE-T Full Duplex ability. 0: link partner without 10BASE-T full duplex ability. 1: link partner with 10BASE-T full duplex ability. Link Partner's 10BASE-T Half Duplex ability. 0: link partner without 10BASE-T ability. 1: link partner with 10BASE-T ability. Link partner select field. Default 00001=IEEE 802.3. Default Val 0 RW Type RO
13
LPRF
0
RO
12,11 10
--LPFC
0 0
RO RO
9
LPT4
0
RO
8
LPTXF
0
RO
7
LPTXH
0
RO
6
LP10F
0
RO
5
LP10H
0
RO
4~0
LPSF
00001
RO
XR6(offset = cch) - ANE, Auto-Negotiation expansion 15~5 4 --PDF reserved Parallel detection fault. 0: no fault detected. 1: a fault detected via parallel detection function. Link Partner's Next Page ability. 0: link partner without next page ability. 1: link partner with next page ability. STE10/100's next Page ability. Always 0; STE10/100 does not support next page ability. Page Received. 0: no new page has been received. 1: a new page has been received. Link Partner Auto-Negotiation ability. 0: link partner has no Auto-Negotiation ability. 1: link partner has Auto-Negotiation ability. 0 0 RO RO/LH*
3
LPNP
0
RO
2 1
NP PR
0 0
RO RO/LH*
0
LPAN
0
RO
LH = High Latching and cleared by reading.
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Table 8. Transceiver registers Descriptions
Bit # Name Descriptions Default Val RW Type
XR7(offset = d0h) - XMC, XCVR Mode control 15~12 11 --LD reserved Long Distance mode of 10BASE-T. 0: normal squelch level. 1: reduced 10Base-T squelch level for extended cable length. reserved 0 0 RO R/W
10~0
---
0
RO
XR8(offset = d4h) - XCIIS, XCVR Configuration information and Interrupt Status 15~10 9 ---SPEED reserved Speed configuration setting. 0: the speed is 10Mb/s. 1: the speed is 100Mb/s. Duplex configuration setting. 0: the duplex mode is half. 1: the duplex mode is full. PAUSE function configuration setting for flow control. 0: PAUSE function is disabled. 1: PAUSE function is enabled Auto-Negotiation Completed Interrupt. 0: Auto-Negotiation has not completed yet. 1: Auto-Negotiation has completed. Remote Fault Detected Interrupt. 0: there is no remote fault detected. 1: remote fault is detected. Link Fail Interrupt. 0: link test status is up. 1: link is down. Auto-Negotiation Acknowledge Received Interrupt. 0: there is no link code word received. 1: link code word is receive from link partner. Parallel Detection Fault Interrupt. 0: there is no parallel detection fault. 1: parallel detection is fault. Auto-Negotiation Page Received Interrupt. 0: there is no Auto-Negotiation page received. 1: auto-negotiation page is received. Receive Error full Interrupt. 0: the receive error number is less than 64. 1: 64 error packets is received. 0 0 RO RO
8
DUPLEX
0
RO
7
PAUSE
0
RO
6
ANC
0
RO/LH*
5
RFD
0
RO/LH*
4
LS
0
RO/LH*
3
ANAR
0
RO/LH*
2
PDF
0
RO/LH*
1
ANPR
0
RO/LH*
0
REF
0
RO/LH*
LH = High Latching and cleared by reading.
XR9(offset = d8h) - XIE, XCVR Interrupt Enable Register 15~7 --reserved
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Table 8. Transceiver registers Descriptions
Bit # 6 Name ANCE Descriptions Auto-Negotiation Completed interrupt Enable. 0: disable Auto-Negotiation completed interrupt. 1: enable auto-negotiation complete interrupt. Remote Fault detected interrupt Enable. 0: disable remote fault detection interrupt. 1: enable remote fault detection interrupt. Link Down interrupt Enable. 0: disable link fail interrupt. 1: enable link fail interrupt. Auto-Negotiation Acknowledge interrupt Enable. 0: disable link partner acknowledge interrupt 1: enable link partner acknowledge interrupt. Parallel Detection Fault interrupt Enable. 0: disable fault parallel detection interrupt. 1: enable fault parallel detection interrupt. Auto-Negotiation Page Received interrupt Enable. 0: disable Auto-Negotiation page received interrupt. 1: enable Auto-Negotiation page received interrupt. RX_ERR full interrupt Enable. 0: disable rx_err full interrupt. 1: enable rx_err interrupt. Default Val 0 RW Type R/W
5
RFE
0
R/W
4
LDE
0
R/W
3
ANAE
0
R/W
2
PDFE
0
R/W
1
ANPE
0
R/W
0
REFE
0
R/W
XR10(offset = dch) - 100CTR, 100BASE-TX Control Register 15,14 13 --DISRER reserved Disable the RX_ERR counter. 0: the receive error counter - RX_ERR is enabled. 1: the receive error counter - RX_ERR is disabled. Auto-Negotiation completed. This bit is the same as bit 5 of XR1. 0: the Auto-Negotiation process has not completed yet. 1: the Auto-Negotiation process has completed. Select peak to peak voltage of receive. 0: receive voltage peak to peak 1.0 VPP 1: receive voltage peak to peak 1.4 VPP. reserved Enable remote loop-back function. 1: enable remote loop-back (CSR6 bits 11 and 10 must be 00). Enable DC restoration. 0: disable DC restoration. 1: enable DC restoration. Enable the conversions between NRZ and NRZI. 0: disable the data conversion between NRZ and NRZI. 1: enable the data conversion of NRZI to NRZ in receiving and NRZ to NRZI in transmitting. reserved. 0 1 R/W R/W 0 R/W
12
ANC
0
RO
11
RXVPP
0
R/W
10 9 8
--ENRLB ENDCR
7
ENRZI
1
R/W
6
---
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Table 8. Transceiver registers Descriptions
Bit # 5 4~2 Name ISOTX CMODE Descriptions Transmit Isolation. When 1, isolate from MII and tx+/-. This bit must be 0 for normal operation Reports current transceiver operating mode. 000: in auto-negotiation 001: 10Base-T half duplex 010: 100Base-TX half duplex 011: reserved 100: reserved 101: 10Base-T full duplex 110: 100Base-TX full duplex 111: isolation, auto-negotiation disable Disable MLT3. 0: the MLT3 encoder and decoder are enabled. 1: the MLT3 encoder and decoder are bypassed. Disable Scramble. 0: the scrambler and de-scrambler is enabled. 1: the scrambler and de-scrambler are disabled. Default Val 0 000 RW Type R/W RO
1
DISMLT
0
R/W
0
DISCRM
0
R/W
5.4 Descriptors and Buffer Management The STE10/100 provides receive and transmit descriptors for packet buffering and management. 5.4.1 Receive descriptor Table 9. Receive Descriptor Table
31 RDES0 RDES1 RDSE2 RDSE3 Own --Control Status Buffer2 byte-count Buffer1 byte-count 0
Buffer1 address (DW boundary) Buffer2 address (DW boundary
Note: 1. Descriptors and receive buffers addresses must be longword aligned
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Table 10. Receive Descriptor Descriptions
Bit# RDES0 31 OWN Own bit 1: indicates that newly received data can be put into this descriptor 0: Host has not yet processed the received data currently in this descriptor. Frame length, including CRC. This field is valid only in a frame's last descriptor. Error summary. Logical OR of the following bits: 0: overflow 1: CRC error 6: late collision 7: frame too long 11: runt packet 14: descriptor error This field is valid only in a frame's last descriptor. Descriptor error. This bit is valid only in a frame's last descriptor. 1: the current valid descriptor is unable to contain the packet being currently received. The packet is truncated. Data type. 00: normal 01: MAC loop-back 10: Transceiver loop-back 11: remote loop-back These bits are valid only in a frame's last descriptor. Runt frame (packet length < 64 bytes). This bit is valid only in a frame's last descriptor. Multicast frame. This bit is valid only in a frame's last descriptor. First descriptor. Last descriptor. Packet Too Long (packet length > 1518 bytes). This bit is valid only in a frame's last descriptor. Late collision. Set when collision is active after 64 bytes. This bit is valid only in a frame's last descriptor Frame type. This bit is valid only in a frame's last descriptor. 0: 802.3 type 1: Ethernet type Receive watchdog (refer to CSR15, bit 4). This bit is valid only in a frame's last descriptor. Default = 0 Dribble bit. This bit is valid only in a frame's last descriptor 1: Packet length is not integer multiple of 8-bit. 1: CRC error. This bit is valid only in a frame's last descriptor 1: Overflow. This bit is valid only in a frame's last descriptor Name Descriptions
30-16 15
FL ES
14
DE
13-12
DT
11 10 9 8 7 6 5
RF MF FS LS TL CS FT
4 3 2 1 0 RDES1 31~26 25
RW reserved DB CE OF
--RER
reserved Receive end of ring. Indicates this descriptor is last, return to base address of descriptor
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Table 10. Receive Descriptor Descriptions
Bit# 24 Name RCH Descriptions Second address chain Used for chain structure, indicating the buffer 2 address is the next descriptor address. Ring mode takes precedence over chained mode reserved Buffer 2 size (DW boundary) Buffer 1 size (DW boundary)
23~22 21~11 10~ 0 RDES2 31~0 RDES3 31~0
--RBS2 RBS1
RBA1
Receive Buffer Address 1. This buffer address should be double word aligned.
RBA2
Receive Buffer Address 2. This buffer address should be double word aligned.
5.4.2 Transmit Descriptor Table 11. Transmit Descriptor Table
31 TDES0 TDES1 TDSE2 TDSE3
Note: 1. Descriptor addresses must be longword alignment
0 Status Control Buffer2 byte-count Buffer1 address Buffer2 address Buffer1 byte-count
Own
Table 12. Transmit Descriptor Descriptions
Bit# TDSE0 31 OWN Own bit 1: Indicates this descriptor is ready to transmit 0: No transmit data in this descriptor. Reserved Under-run count Reserved Error summary. Logical OR of the following bits: 1: under-run error 8: excessive collision 9: late collision 10: no carrier 11: loss carrier 14: jabber time-out Transmit jabber time-out Name Descriptions
30-24 23-22 21-16 15
--UR --ES
14
TO
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Table 12. Transmit Descriptor Descriptions
Bit# 13-12 11 10 9 8 7 6-3 2 1 0 TDES1 31 30 29 28,27 26 25 24 23 22 21-11 10-0 TDES2 31~0 TDES3 31~0 BA2 Buffer Address 2. No alignment limitations imposed on the transmission buffer address. BA1 Buffer Address 1. No alignment limitations imposed on the transmission buffer address. IC LS FS --AC TER TCH DPD --TBS2 TBS1 Interrupt completed Last descriptor First descriptor Reserved Disable add CRC function End of Ring 2nd address chain. Indicates that the buffer 2 address is the next descriptor address Disable padding function Reserved Buffer 2 size Buffer 1 size Name ----LO NC LC EC HF CC ----UF DE Reserved Loss of carrier No carrier Late collision Excessive collision Heartbeat fail Collision count Reserved Under-run error Deferred Descriptions
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6.0 FUNCTIONAL DESCRIPTIONS 6.1 Initialization Flow Figure 4. Initialization Flow of STE10/100
Search NIC
Get base IO address Get IRQ value
Reset MAC (CSR0) Reset PHY (XR0)
Need set media type?
Yes
(Force Media) Program the media type to XR0
No Read EEPROM from CSR9 Set Physical adress (CSR25, 26)
Need set Multicast?
Yes
Set Multicast address table (CSR27, 28)
No A
Prepare Transmit descriptor and buffer Prepare Receive descriptor and buffer
Install NIC ISR function
Open NIC interrupt Enable Tx & Rx functions
END
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6.2 Network Packet Buffer Management 6.2.1 Descriptor Structure Types During normal network transmit operations, the STE10/100 transfers the data packets from transmit buffers in the host's memory to the STE10/100's transmit FIFO. For receive operations, the STE10/100 transfers the data packet from its receive FIFO to receive buffers in the host's memory. The STE10/100 makes use of descriptors, data structures which are built in host memory and contain pointers to the transmit and receive buffers and maintain packet and frame parameters, status, and other information vital to controlling network operation. There are two types of structures employed to group descriptors, the Ring and the Chain, both supported by the STE10/100 and shown below. The selection of structure type is controlled by RCH (RDES1 bit 24) and TCH (TDES1 bit 24). The transmit and receive buffers reside in the host's memory. Any buffer can contain either a complete or partial packet. A buffer may not contain more than one packet. s Ring structure: There are two buffers per descriptor in the ring structure. Support receive early interrupt. Figure 5. Ring structure of frame buffer
Descriptor CSR3 or CSR4 Descriptor Pointer own
Length 2 Length 1
Data Buffer Data Length 1
Buffer1 pointer Buffer2 pointer . . . . . . . End of Ring
Data
Length 2
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s
Chain structure: There is only one buffer per descriptor in chain structure.
Figure 6. Chain structure of frame buffer
CSR3 or CSR4 Descriptor Pointer
Descriptor own --Length 1
Data Buffer Data Length 1
Buffer1 pointer Next pointer
own --Length 2
Buffer1 pointer Next pointer Data Length 2
own --Length 3
Buffer1 pointer Next pointer . . .
Data . . .
Length 3
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6.2.2 Descriptor Management OWN bit = 1, ready for network side access OWN bit = 0, ready for host side access s Transmit Descriptors Figure 7. Transmit descriptor management
Descriptor Ring
next packet to be transmitted own bit=1, Packet 1 and packet 2 are ready to transmit
0
Length 2 Length 1
Buffer 1 pointer Buffer 2 pointer 1
Data Buffer
packet1
data
1
packet1
data
1
packet2
empty descriptor pointer
0
* * * end of ring
0
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s
Receive Descriptors
Figure 8. Receive descriptor management
0
Packet 2
own bit=1, next descriptor ready for incoming packet 1
Data ff
1
1
filled descriptor pointer 0
Packet 1
* * * 0
end of ring
Packet 2
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6.3 Transmit Scheme and Transmit Early Interrupt 6.3.1 Transmit flow Figure 9. The flow of packet transmit is shown as below.
Initialize descriptor Place data in host memory Set Own bit to 1 Write Tx demand poll command
Exit
Own = 0
STE10/100 checks descriptor Own = 1
Transfer data to Tx FIFO
Deferring OR data less than Tx threshold?
Transmit data across line
Back-off
Collision occurred?
Write descriptor Generate interrupt
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6.3.2 Transmit pre-fetch data flow
s s s
Transmit FIFO size=2K-byte two packets in the FIFO at the same time meet the transmit min. back-to-back
Figure 10. Transmit data flow of pre-fetch data
place the 1st packet data into host memory issue transmit demand FIFO-to-host memory operation (1st packet) Transmit enable place the 2nd packet data into host memory check point FIFO-to-host memory operation (2nd packet) place the 3rd packet data into host memory check point FIFO-to-host memory operation (3rd packet)
1st packet is transmitted, check the 3rd packet 1st packet check the next packet 2nd packet transmit threshold IFG
time
: handled by driver
: handled by STE10/100
6.3.3 Transmit early interrupt Scheme Figure 11. Transmit normal interrupt and early interrupt comparison
Host to TX-FIFO Memory Operation Transmit data from FIFO to Media Normal Interrupt after Transmit Completed Driver return buffer to upper layer Early Interrupt after Host to TXFIFO Operation Completed Driver return buffer to upper layer
time The saved time when transmit early interrupt is implemented
: handled by driver
: handled by STE10/100
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6.4 Receive scheme and Receive early interrupt scheme The following figure shows the difference of timing without early interrupt and with early interrupt. Figure 12. Receive data flow (without early interrupt and with early interrupt)
incoming packet receive FIFO operation FIFO-to-host memory operation interrupt driver read header higher layer process driver read the rest data receive early interrupt driver read header(early) higher layer process(early) driver read the rest data finish time finish time
time
: without early interrupt
: with early interrupt
Figure 13. Detailed Receive Early interrupt flow
The size of 1st descriptor is programmed as the header size in advance 1st descriptor full
2nd descriptor
FIFO-to-host memory i receive early driver read higher layer driver read the rest
issue 2nd interrupt at end of packet
time
finish i
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6.5 Network Operation 6.5.1 MAC Operation The MAC (Media Access Control) portion of STE10/100 incorporates the essential protocol requirements for operating as an IEEE802.3 and Ethernet compliant node. s Format
Field Preamble Start Frame Delimiter Destination Address Source Address Length/Type A 7-byte field of (10101010b) A 1-byte field of (10101011b) A 6-byte field A 6-byte field A 2-byte field indicated the frame is in IEEE802.3 format or Ethernet format. IEEE802.3 format: 0000H ~ 05DCH for Length field Ethernet format: 05DD ~ FFFFH for Type field *46 ~ 1500 bytes of data information A 32-bit cyclic redundancy code for error detection Description
Data CRC
*Note: If padding is disabled (TDES1 bit 23), the data field may be shorter than 46 bytes.
s
Transmit Data Encapsulation The differences between transmit data encapsulation and a MAC frame while operating in 100BASETX mode are listed as follows: 1. The first byte of the preamble is replaced by the JK code according to IEE802.3u, clause 24. 2. After the CRC field of the MAC frame, the STE10/100 will insert the TR code according to IEE802.3u, clause 24. Receive Data Decapsulation When operating in 100BASE-TX mode the STE10/100 detects a JK code in a preamble as well as a TR code at the packet end. If a JK code is not detected, the STE10/100 will abort the reception of the frame and wait for a new JK code detection. If a TR code is not detected, the STE10/100 will report a CRC error. Deferring The Inter-Frame Gap (IFG) time is divided into two parts: 1.IFG1 time (64-bit time): If a carrier is detected on the medium during this time, the STE10/100 will reset the IFG1 time counter and restart to monitor the channel for an idle again. 2.IFG2 time (32-bit time): After counting the IFG2 time the STE10/100 will access the channel even though a carrier has been sensed on the network. Collision Handling The scheduling of re-transmissions are determined by a controlled randomization process called "truncated binary exponential back-off". At the end of enforcing a collision (jamming), the STE10/100 delays before attempting to re-transmit the packet. The delay is an integer multiple of slot time. The number of slot times to delay before the nth re-transmission attempt is chosen as a uniformly distributed integer r in the range: 0 * r < 2k where k = min(n, 10)
s
s
s
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6.5.2 Transceiver Operation The transceiver portion of the STE10/100 integrates the IEEE802.3u compliant functions of PCS (physical coding sub-layer), PMA (physical medium attachment) sub-layer, and PMD (physical medium dependent) sub-layer for 100BASE-TX, and the IEEE802.3 compliant functions of Manchester encoding/decoding and transceiver for 10BASE-T. All the functions and operating schemes are described in the following sections. s 100BASE-TX Transmit Operation For 100BASE-TX transmissions, the STE10/100 transceiver provides the transmission functions of PCS, PMA, and PMD for encoding of MII data nibbles into five-bit code-groups (4B/5B), scrambling, serialization of scrambled code-groups, converting the serial NRZ code into NRZI code, converting the NRZI code into MLT3 code, and then driving the MLT3 code into the category 5 Unshielded Twisted Pair cable through an isolation transformer with the turns ratio of 1.414 : 1.
s
Data code-groups Encoder: In normal MII mode applications, the transceiver receives nibble type 4B data via the TxD0~3 inputs of the MII. These inputs are sampled by the transceiver on the rising edge of Tx-clk and passed to the 4B/5B encoder to generate the 5B code-group used by 100BASE-TX. Idle code-groups: In order to establish and maintain the clock synchronization, the transceiver must keep transmitting signals to medium. The transceiver will generate Idle code-groups for transmission when there is no actual data to be sent by MAC. Start-of-Stream Delimiter-SSD (/J/K/): In a transmission stream, the first 16 nibbles comprise the MAC preamble. In order to let a network partner delineate the boundary of a data transmission sequence and to authenticate carrier events, the transceiver will replace the first 2 nibbles of the MAC preamble with /J/K/ code-groups. End-of-Stream Delimiter-ESD (/T/R/): In order to indicate the termination of normal data transmissions, the transceiver will insert 2 nibbles of /T/R/ code-group after the last nibble of the FCS. Scrambling: All the encoded data (including the idle, SSD, and ESD code-groups) is passed to the data scrambler to reduce EMI by spreading the power spectrum using a 10-bit scrambler seed loaded at the beginning. Data conversion of Parallel to Serial, NRZ to NRZI, NRZI to MLT3: After being scrambled, the 5B type transmission data at 25MHz will be converted to a 125HMz serial bit stream by the parallel-to-serial function. The bit stream will be further converted from NRZ to NRZI format, unless the conversion function is bypassed by clearing ENRZI (bit 7 of XR10) to 0. After NRZI conversion, the NRZI bit stream is passed through MLT3 encoder to generate the TP-PMD specified MLT3 code. By using MLT3 code, the frequency and energy content of the transmission signal is reduced in the UTP, making the system more easily compliant to FCC EMI specifications. Wave-Shaper and Media Signal Driver: In order to reduce the energy of the harmonic frequency of transmission signals, the transceiver provides a wave-shaper prior the line driver to smooth the rising/ falling edge of transmission signals while maintaining the waveforms' symmetry. The 100BASE-TX and 10BASE-T wave-shaped signals are both passed to the same media signal driver. This can simplify system design by employing a single external magnetic connection. 100BASE-TX Receiving Operation For 100BASE-TX receiving operation, the transceiver provides the receiving functions of PMD, PMA, and PCS for incoming data signals through category 5 UTP cable and an isolation transformer with a 1:1 turns ratio. The receive transceiver portion includes the adaptive equalizer and baseline wander, MLT3 to NRZI data conversion, NRZI to NRZ conversion, serial to parallel conversion, a PLL for clock and data recovery, de-scrambler, and the 5B/4B decoder. Adaptive Equalizer and Baseline Wander: High speed signals over unshielded (or shielded) twisted pair cable will experience attenuation and phase shift. These effects depend on the signal frequency, cable type, cable length and the cable connectors. Robust circuits in the transceiver provide reliable adaptive equalizer and baseline wander compensation for amplitude attenuation and phase shift due to
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transmission line parasitics.
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MLT3 to NRZI Decoder and PLL for Data Recovery: Following adaptive equalizer, baseline wander, the transceiver converts the resulting MLT3 to NRZI code, which is passed to the Phase Lock Loop circuits in order to extract the synchronous clock and the original data. Data Conversions of NRZI to NRZ and Serial to Parallel: After the data is recovered, it will be passed to the NRZI-to-NRZ converter to produce a 125MHz serial bit stream. This serial bit stream will be packed to parallel 5B type for further processing. The NRZI to NRZ conversion may be bypassed by clearing ENRZI (bit 7 of XR10) to 0. De-scrambling and Decoding of 5B/4B: The parallel 5B type data is passed to the de-scrambler and 5B/4B decoder to restore it to its original MII nibble representation. Carrier sensing: The Carrier Sense (CRS) signal is asserted when the transceiver detects any 2 noncontiguous zeros within any 10-bit boundary of the receiving bit stream. CRS is de-asserted when ESD code-group or Idle code-group is detected. In half duplex mode, CRS is asserted during packet transmission or receive; in full duplex mode, CRS is asserted only during packet reception. 10BASE-T Transmission Operation The parallel-to-serial converter, Manchester Encoder, Link test, Jabber and the transmit wave-shaper and line driver functions described in the section of "Wave-Shaper and Media Signal Driver" of "100BASE-T Transmission Operation" are also provided for 10BASE-T transmission. Additionally, Collision detection and SQE test for half duplex application are provided. 10BASE-T Receive Operation Carrier sense function, receiving filter, PLL for clock and data recovery, Manchester decoder, and serial to parallel converter functions are provided to support 10BASE-T reception. Loop-back Operation of transceiver The transceiver provides internal loop-back (also called transceiver loop-back) operation for both 100BASE-TX and 10BASE-T operation. The loop-back function can be enabled by setting XLBEN (bit 14 of XR0) to 1. In loop-back mode, the TX and RX lines are isolated from the media. The transceiver also provides remote loop-back operation for 100BASE-TX operation. The remote loop-back operation can be enabled by setting ENRLB (bit 9 of XR10) to 1. In 100BASE-TX internal loop-back operation, the data is routed from the transmit output of NRZ-toNRZI converter and looped back to the receive input of NRZI-to-NRZ converter. In 100BASE-TX remote loop-back operation, data is received from RX pins and passed through the receive path to the output of the data and clock recovery section, and then looped back to the input of the NRZI-to-MLT3 converter and out to the medium via the transmit line drivers. In 10BASE-T loop-back operation, the data is passed through the transmit path to the output of the Manchester encoder and then looped back into the input of the Phase Lock Loop circuit in the receive path. Full Duplex and Half Duplex Operation of Transceiver The transceiver can operate in either full duplex or half duplex network applications. In full duplex, both transmission and reception can take place simultaneously. In full duplex mode, collision (COL) signal is ignored and carrier sense (CRS) signal is asserted only when the transceiver is receiving. In half duplex mode, transmission and reception can not take place simultaneously. In half duplex mode, the collision signal is asserted when transmitted and received signals collide, and carrier sense is asserted during both transmission and reception. Auto-Negotiation Operation The Auto-Negotiation function provides the means to exchange information between the transceiver and the network partner to automatically configure both to take maximum advantage of their abilities. The Auto-Negotiation function is controlled by ANEN (bit 12 of XR0). During Auto-Negotiation information is exchanged with the network partner using Fast Link Pulses
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(FLPs) - a burst of link pulses. There are 16 bits of signaling information contained in the link pulses which advertise to the remote partner the capabilities which are represented by the contents of ANA (register XR4). According to this information the partners find out their highest common capabilities by following the priority sequence listed below: 1. 100BASE-TX full duplex 2. 100BASE-TX half duplex 3. 10BASE-T full duplex 4. 10BASE-T half duplex During power-up or reset, if Auto-Negotiation is enabled, the FLPs will be transmitted and the Auto-Negotiation function will proceed. Otherwise, Auto-Negotiation will not occur until ANEN (bit 12 of XR0) is set to 1. When the Auto-Negotiation is disabled, then Network Speed and Duplex Mode are selected by programming the XR0 register. Power Down Operation The transceiver is designed with a power-down feature which can reduce power consumption significantly. Since the power supply of the 100BASE-TX and 10BASE-T circuits are separate, the transceiver can turn off the circuit of either the 100BASE-TX or 10BASE-T when the other is active.
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6.5.3 Flow Control in Full Duplex Application The PAUSE function is used to inhibit transmission of data frames for a specified period of time. The STE10/ 100 supports the full duplex protocol of IEEE802.3x. To support the PAUSE function, the STE10/100 implements the MAC Control Sub-layer functions to decode the MAC Control frames received from MAC control clients and to execute the relative requests accordingly. When Full Duplex mode and the PAUSE function are selected after Auto-Negotiation completes (refer to the configuration of XR8), the STE10/100 will enable the PAUSE function for flow control in a full duplex application. In this section we will describe how the STE10/100 implements the PAUSE function. s MAC Control Frame and PAUSE Frame Figure 14. MAC Control Frame Format
6 Octets 6 Octets 2 Octets 2 Octets (minFrameSize - 160) / 8 Octets
Destination Address Source Address Length/Type = 88-08h MAC Control Opcode MAC Control Parameter Reserved(pads with zeroes)
The MAC Control frame is distinguished from other MAC frames only by its Length/Type field identifier. The MAC Control Opcode defined in MAC Control Frame format for th PAUSE function is 0001h, and the PAUSE time is specified in the MAC Control Parameters field with 2 Octets, representing an unsigned integer, in units of Slot-Times. The range of possible PAUSE times is 0 to 65535 Slot-Times. A valid PAUSE frame issued by a MAC control client (e.g., a switch or a bridge) would contain: s The destination address, set to the globally assigned 48 bit mulitcast address 01-80-C2-00-00-01, or to the unicast address to which the MAC control client requests to inhibit its transmission of data frames.
s
The MAC Control Opcode field set to 0001h.
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2 Octets of PAUSE time specified in the MAC Control parameter field to indicate the length of time for which the destination is requested to inhibit data frame transmission.
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Receive Operation for PAUSE function Upon reception of a valid MAC Control frame, the STE10/100 will start a timer for the length of time specified by the MAC Control Parameters field. When the timer value reaches zero, the STE10/100 exits the PAUSE state. However, a PAUSE frame will not affect the transmission of a frame that has been submitted to the MAC (i.e., once a transmit out of the MAC is begun, it can't be interrupted). Conversely, the STE10/100 will not begin to transmit a frame more than one slot-time after valid PAUSE frame is received a with a non-zero PAUSE time. If the STE10/100 receives a PAUSE frame with a zero PAUSE time value, the STE10/100 exits the PAUSE state immediately.
Figure 15. PAUSE operation receive state diagram Opcode = PAUSE Function
Wait for Transmission Completed
transmission_in_progress = false * DA = (01-80-C2-00-00-01 + Phys-address)
DA (01-80-C2-00-00-01 + Phys-address)
PAUSE FUNCTION
n_slots_rx = data [17:32] Start pause_timer (n_slots_rx * slot_time) UCT
END PAUSE
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6.6 LED Display Operation The STE10/100 provides 2 LED display modes; the detailed descriptions of their operation are described in the PIN Description section. s First mode - 3 LED displays: 100Mbps (on) or 10Mbps (off) Link (Remains on when link ok) or Activity (Blinks at 10Hz when receiving or transmitting collision-free)
s
FD (Remains on when in Full duplex mode) or Collision (Blinks at 20Hz when collidions detected) Second mode - 4 LED displays: 100 Link (On when 100M link ok) 10 Link (On when 10M link ok) Activity (Blinks at 10Hz when receiving or transmitting) FD (Remains on when in Full duplex mode) or Collision (Blinks at 20Hz when collisions detected)
6.7 Reset Operation 6.7.1 Reset whole chip There are two ways to reset the STE10/100: Hardware reset via RST# pin (to ensure proper reset operation, the RST# signal should be asserted at least 100ms); and software reset via SWR (bit 0 of CSR0) being set to 1 (the STE10/100 will reset all circuits, set registers to their default values, and will clear SWR. 6.7.2 Reset Transceiver only When XRST (bit 15 of XR0) is set to 1, the transceiver will reset its circuits, will initialize its registers to their default values, and clear XRST. 6.8 Wake on LAN Function The STE10/100 can assert a signal to wake up the system when it has received a Magic Packet from the network. The Wake on LAN operation is described as follow. s The Magic Packet format: Valid destination address that can pass the address filter of the STE10/100 The payload of frame must include at least 6 contiguous `FF' followed immediately by 16 repetitions of IEEE address. The frame can contain multiple `six FF + sixteen IEEE address' pattern.
s
Valid CRC The Wake on LAN operation The Wake on LAN enable function is controlled by WOL (bit 18 of CSR18), which is loaded from EEPROM after reset or programmed by driver software. If WOL is set and the STE10/100 receives a Magic Packet, it will assert the PME# signal (active low) to indicate reception of a wake up frame and will set the PME status bit (bit 15 of CSR20).
6.9 ACPI Power Management Function The STE10/100 has a built-in capability for Power Management (PM) which is controlled by the host system The STE10/100 will provide: s Compatibility with Device Class Power Management Reference Specification
s s s
Network Device Class, Draft proposal v0.9, October 1996 Compatibility with ACPI, Rev 1.0, December 22, 1996 Compatibility with PCI Bus Power Management Interface Specification, Rev 1.0, January 6, 1997
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Compatibility with AMD Magic PacketTM Technology.
6.9.1 Power States
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DO (Fully On) In this state the STE10/100 operates with full functionality and consumes normal power. While in the D0 state, if the PCI clock is lower than 16MHz, the STE10/100 may not receive or transmit frames properly. D1, D2, and D3hot In these states, the STE10/100 doesn't respond to any accesses except configuration space and full function context in place. The only network operation the STE10/100 can initiate is a wake-up event. D3cold (Power Removed) In this state all function context is lost. When power is restored, a PCI reset must be asserted and the function will return to D0. D3hot (Software Visible D3) When the STE10/100 is brought back to D0 from D3hot the software must perform a full initialization. The STE10/100 in the D3hot state responds to configuration cycles as long as power and clock are supplied. This requires the device to perform an internal reset and return to a power-up reset condition without the RST# pin asserted.
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Table 13. Power Stage
Device State D0 PCI Bus State B0 Function Context Full function context in place Configuration maintained. No Tx and Rx except wake-up events Configuration maintained. No Tx and Rx Configuration lost, full initialization required upon return to D0 All configuration lost. Power-on defaults in place on return to D0 Clock Full speed Power Full power Supported Actions to Function Any PCI transaction PCI configuration access Supported Actions from Function Any PCI transaction or interrupt Only wake-up events
D1
B0, B1
Stopped to Full speed
D2
B0, B1, B2 B0, B1, B2 B3
Stopped to Full speed Stopped to Full speed No clock No power
PCI configuration access(B0, B1) PCI configuration access(B0, B1) Power-on reset
D3hot
D3cold
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7.0 GENERAL EEPROM FORMAT DESCRIPTION Table 14. Connection Type Definition
Offset 0 2 3 4 8 E
Length 2 1 1 4 6 1 STE10/100 Signature: 0x81, 0x09
Description
Format major version: 0x02, old ROM format version 0x01 is for STE10/100-MAC only. Format minor version: 0x00 Reserved IEEE network address: ID1, ID2, ID3, ID4, ID5, ID6 IEEE ID checksum1: Sm0=0, carry=0 SUM=Sm6 where Smi=(Smi-1<<1)+(carry from shift)+IDi IEEE ID checksum2: Reserved, should be zero. PHY type, 0xFF: Internal PHY (STE10/100 only) Reserved, should be zero. Default Connection Type, see Table 15 Reserved, should be zero. Flow Control Field, 00: Disable Flow Control function, 01: Enable Flow Control function PCI Device ID. PCI Vendor ID. PCI Subsystem ID. PCI Subsystem Vendor ID. MIN_GNT value. MAX_LAT value. Cardbus CIS pointer. CSR18 (CR) bit 31-16 recall data. Reserved, should be zero. CheckSum, the least significant two bytes of FCS for data stored in offset 0..7D of EEPROM
F 10 11 12 14 1F
1 1 1 2 0B 1
20 22 24 26 28 29 2A 2E 30 7E
2 2 2 2 1 1 4 2 4E 2
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Table 15. Connection Type Definition
0xFFFF 0x0100 0x0200 0x0400 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0010 0x0013 0x0015 Software Driver Default Auto-Negotiation Power-on Auto-detection Auto Sense 10BaseT BNC AUI 100BaseTx 100BaseT4 100BaseFx 10BaseT Full Duplex 100BaseTx Full Duplex 100BaseFx Full Duplex
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8.0 ELECTRICAL SPECIFICATIONS AND TIMINGS Table 16. Absolute Maximum Ratings
Parameter Supply Voltage(Vcc) Input Voltage Output Voltage Storage Temperature Ambient Temperature ESD Protection -0.5 V to 7.0 V -0.5 V to VCC + 0.5 V -0.5 V to VCC + 0.5 V -65 C to 150 C(-85F to 302F) 0C to 70C(32F to 158F) 2000V Value
Table 17. General DC Specifications
Symbol General DC Vcc Icc Supply Voltage Power Supply 4.75 300 5.25 V mA Parameter Test Condition Min. Typ. Max. Units
PCI Interface DC Specfications Vilp Vihp Iilp Iihp Volp Vohp Cinp Cclkp Cidsel Lpinp Input LOW Voltage Input HIGH Voltage Input LOW Leakage Current Input HIGH Leakage Current Output LOW Voltage Output HIGH Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capacitance Pin Inductance Vin = .8V Vin = 2.0V Iout =3mA/6mA Iout =-2mA -0.5 2.0 -10 -10 . 2.4 5 5 5 N/A 8 8 8 0.8 5.5 10 10 .55 V V A A V V pF pF pF nH
Flash/EEPROM Interface DC Specifications Vilf Vihf Iif Volf Vohf Cinf Input LOW Voltage Input HIGH Voltage Input Leakage Current Output LOW Voltage Output HIGH Voltage Input Pin Capacitance Iout=3mA,6mA Iout=-2mA 2.4 5 8 -0.5 2.0 -10 0.8 5.5 10 .55 V V A V V pF
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Table 17. General DC Specifications
Symbol Parameter Test Condition Min. Typ. Max. Units
10BASE-T Voltage/Current Characteristics Rid10 Vida10 Vidr10 Vicm10 Vod10 Icct10 Input Differential Resistance Input Differential Accept Peak Voltage Input Differential Reject Peak Voltage Input Common Mode Voltage Output Differential Peak Voltage Line Driver Supply 2200 TBD DC 5MHz ~ 10MHz 5MHz ~ 10MHz 585 0 TBD 2800 TBD 3100 585 k mV mV V V mA
100BASE-TX Voltage/Current Characteristics Rid100 Vida100 Vidr100 Input Differential Resistance Input Differential Accept Peak Voltage Input Differential Reject Peak Voltage 200 0 TBD 950 TBD 1050 TBD 1000 200 k mV mV V V mA
Vicm100 Input Common Mode Voltage Vod100 Icct100 Output Differential Peak Voltage Line Driver Supply
Table 18. AC Specifications
Symbol Parameter Test Condition Min. Typ. Max. Units
PCI Signaling AC Specifications Ioh(AC) Iol(AC) Icl Switching Current High Switching Current Low Low Clamp Current Vout=.7Vcc Vout=.18Vcc -3Tr Tf
Unloaded Output Rise Time Unloaded Output Fall Time
V/ns V/ns
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8.1 Timing Specifications Table 19. PCI Clock Specifications
Symbol Tc Th Tl Parameter Clock Cycle Time Clock High Time Clock Low Time Clock Slew Rate Test Condition Min. 30 11 11 1 Typ. Max. 50 --4 Units ns ns ns V/ns
Figure 16. PCI Clock Waveform
2.4V 2.0V 2V pick to pick 1.5V 0.8V
0.4V
Th
Tl
Tc
Table 20. X1 Specifications
Symbol TX1d TX1p TX1t Parameter X1 Duty Cycle X1 Period X1 Tolerance Test Condition Min. 45 Typ. 50 30 Max. 55 Units % ns PPM
Table 21. PCI Timing
Symbol Tval Parameter Clock to Signal Valid Delay (bussed signals) Test Condition Min. 2 2 2 28 Typ. Max. 11 11 Units ns ns ns ns
Tval(ptp) Clock to Signal Valid Delay (point to point) Ton Toff Float to Active Delay Active to Float Delay
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Table 21. PCI Timing
Symbol Tsu Tsu(ptp) Th Th Trst Trst-clk Trst-off Parameter Input Set up Time to Clock (bussed signals) Input Set up Time to Clock (point to point) Input Hold Time from Clock Input Hold Time from Clock Reset Active Time after Power Stable Reset Active Time after CLK Stable Reset Active to Output Float delay Test Condition Min. 7 10,12 0 0 1 100 40 Typ. Max. Units ns ns ns ns ms s ns
Figure 17. PCI Timings
1.5V CLK
2.4V 0.4V
Tval
OUTPUT Delay 1.5V
Tri-state OUTPUT
Ton Toff Tsu Th
INPUT 1.5V
1.5V
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Table 22. Flash Interface Timings
Symbol Tfcyc Tfce Tfce Tfoe Tfdf Tfas Tfah Tfcs Tfch Tfds Tfdh Tfwpw Tfwph Tfasc Tfahc Parameter Read/Write Cycle Time Address to Read Data Setup Time CS# to Read Data Setup Time OE# Active to Read Data Setup Time OE# Inactive to Data Driven Delay Time Address Setup Time before WE# Address Hold Time after WE# CS# Setup Time before WE# Address Hold Time after WE# Data Setup Time Data Hold Time Write Pulse Width Write Pulse Width High Address Setup Time before CS# Address Hold Time after CS# Test Condition Min. Typ. Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Figure 18. Flash write timings
Tfcyc
ADDRESS Tfasw Tfasc Tfah Tahw
CS# Tfcsh Tfcss Tfwpw
WE# Tfwph Tfds DATA Tfdh
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Figure 19. Flash read timings
ADDRESS Tfcyc
CS# Tfce OE#
Tfoe Tfdf Tfasd
DATA
Table 23. EEPROM Interface Timings
Symbol Tscf Tecss Tecsh Tedts Tedth Tecsl Parameter Serial Clock Frequency Delay from CS High to SK High Delay from SK Low to CS Low Setup Time of DI to SK Hold Time of DI after SK CS Low Time Test Condition Min. Typ. Max. Units
Figure 20. Serial EEPROM timing
CS Tecss CLK Tecsh Tecsl
Tedts
Tedth
DI
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Table 24. 10BASE-T Normal Link Pulse(NLP) Timings Specifications
Symbol NLP Width NLP Period Parameter 10Mbps 10Mbps 8 Test Condition Min. Typ. 100 24 Max. Units ns ms
Figure 21. Normal Link Pulse timings
Tnpw
Tnpc
Table 25. Auto-Negotiation Fast Link Pulse(FLP) Timings Specifications
Symbol Tflpw FLP Width Clock pulse to clock pulse period Clock pulse to Data pulse period Number of pulses in one burst Burst Width FLP Burst period 8 111 55.5 17 2 16 24 Parameter Test Condition Min. Typ. 100 125 62.5 139 69.5 33 Max. Units
Figure 22. Fast Link Pulse timing
Table 26. 100BASE-TX Transmitter AC Timings Specification
Symbol Tjit Parameter TDP-TDN Differential Output Peak Jitter Test Condition Min. Typ. Max. 1.4 Units ps
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DIM. MIN. A A1 A2 b C D E e HD HE L L1 ZD ZE ccc Angle 0.73 0.25 2.57 0.13 0.13
mm TYP. 3.04 0.33 2.71 2.87 0.28 0.23 20 14 0.5 23.2 17.2 0.88 1.60 0.75 0.75 0.12 0(min.), 7(max.) 1/03 0.029 MAX. 3.40 0.010 0.101 0.005 0.005 MIN.
inch TYP. 0.12 0.013 0.107 0.113 0.011 0.009 0.787 0.551 0.02 0.913 0.677 0.035 0.063 0.03 0.03 0.005 0.041 MAX. 0.134
OUTLINE AND MECHANICAL DATA
L dimension is measured at gauge plane at 0.25 above the seating plane
PQFP128 (14x20x2.7mm)
HD D A ZD
CDC
A2 A1
102 103
65 64
ZE
0.12 .005
M
C
A -B
S
DS
b E HE
PIN 1 ID
128 1 e 38
39 C
L1
0.7 DEGREES
PQF128CM
0.25
L
GAGE PLANE
May 1999
1020818
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 1999 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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